From 329f3a849fe1aaffe75c2295b943368544484ad5 Mon Sep 17 00:00:00 2001
From: YuhangQ <i@yuhangq.com>
Date: Thu, 9 Mar 2023 14:54:23 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E9=87=8F=20STEM-INC=20=E5=AE=9E?=
 =?UTF-8?q?=E9=AA=8C?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 atpg                               |    Bin 77680 -> 74736 bytes
 check.log                          |     46 +-
 exp_result/ATPG-LS_b01.bench.txt   |    133 +-
 exp_result/ATPG-LS_b02.bench.txt   |      7 -
 exp_result/ATPG-LS_b03.bench.txt   |    158 +-
 exp_result/ATPG-LS_b04.bench.txt   |  38575 +++-
 exp_result/ATPG-LS_b06.bench.txt   |     80 +-
 exp_result/ATPG-LS_b07.bench.txt   |  54000 +++++-
 exp_result/ATPG-LS_b08.bench.txt   |   9235 +-
 exp_result/ATPG-LS_b09.bench.txt   |   2478 +-
 exp_result/ATPG-LS_b10.bench.txt   |   1266 +-
 exp_result/ATPG-LS_b11.bench.txt   |  25388 ++-
 exp_result/ATPG-LS_b12.bench.txt   |   2931 +
 exp_result/ATPG-LS_b13.bench.txt   | 108874 ++++++++++-
 exp_result/ATPG-LS_b20.bench.txt   |     69 +
 exp_result/ATPG-LS_b21.bench.txt   |     66 +
 exp_result/ATPG-LS_b22.bench.txt   |     12 +
 exp_result/ATPG-LS_c1355.bench.txt |  55649 ++----
 exp_result/ATPG-LS_c17.bench.txt   |      4 +-
 exp_result/ATPG-LS_c1908.bench.txt |  25848 ++-
 exp_result/ATPG-LS_c2670.bench.txt |  13745 +-
 exp_result/ATPG-LS_c3540.bench.txt |   1818 +-
 exp_result/ATPG-LS_c432.bench.txt  | 265492 +++++++++++++++++---------
 exp_result/ATPG-LS_c499.bench.txt  |  25118 +--
 exp_result/ATPG-LS_c5315.bench.txt |   2424 +
 exp_result/ATPG-LS_c6288.bench.txt |    996 +-
 exp_result/ATPG-LS_c7552.bench.txt |   2425 +-
 exp_result/ATPG-LS_c880.bench.txt  |   2978 +-
 ls.cpp                             |      2 +-
 report/atpg-ls-动态增量.txt        |     30 +
 run_exp.py                         |      6 +-
 31 files changed, 468404 insertions(+), 171449 deletions(-)
 delete mode 100644 exp_result/ATPG-LS_b02.bench.txt
 create mode 100644 report/atpg-ls-动态增量.txt

diff --git a/atpg b/atpg
index 771043cae3b5eb04ba0718c615693c90cf92dc25..8ca5c145d33b479e4df9787207951d502b3c28cb 100755
GIT binary patch
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diff --git a/check.log b/check.log
index c2859ca..52da0ce 100644
--- a/check.log
+++ b/check.log
@@ -1,26 +1,26 @@
-[1/26] 任务 ./benchmark/b22.bench
-[2/26] 任务 ./benchmark/b17.bench
-[3/26] 任务 ./benchmark/c5315.bench
-[4/26] 任务 ./benchmark/b13.bench
-[5/26] 任务 ./benchmark/b03.bench
+[1/26] 任务 ./benchmark/c17.bench
+[2/26] 任务 ./benchmark/b06.bench
+[3/26] 任务 ./benchmark/b01.bench
+[4/26] 任务 ./benchmark/b03.bench
+[5/26] 任务 ./benchmark/b09.bench
 [6/26] 任务 ./benchmark/c880.bench
 [7/26] 任务 ./benchmark/b10.bench
-[8/26] 任务 ./benchmark/c6288.bench
-[9/26] 任务 ./benchmark/c1355.bench
-[10/26] 任务 ./benchmark/b20.bench
-[11/26] 任务 ./benchmark/c17.bench
-[12/26] 任务 ./benchmark/b07.bench
-[13/26] 任务 ./benchmark/b01.bench
-[14/26] 任务 ./benchmark/c432.bench
-[15/26] 任务 ./benchmark/b11.bench
-[16/26] 任务 ./benchmark/b08.bench
-[17/26] 任务 ./benchmark/c3540.bench
-[18/26] 任务 ./benchmark/c2670.bench
-[19/26] 任务 ./benchmark/b09.bench
-[20/26] 任务 ./benchmark/c7552.bench
-[21/26] 任务 ./benchmark/b04.bench
+[8/26] 任务 ./benchmark/b08.bench
+[9/26] 任务 ./benchmark/c499.bench
+[10/26] 任务 ./benchmark/c1355.bench
+[11/26] 任务 ./benchmark/c3540.bench
+[12/26] 任务 ./benchmark/c1908.bench
+[13/26] 任务 ./benchmark/b11.bench
+[14/26] 任务 ./benchmark/c6288.bench
+[15/26] 任务 ./benchmark/c2670.bench
+[16/26] 任务 ./benchmark/b21.bench
+[17/26] 任务 ./benchmark/b13.bench
+[18/26] 任务 ./benchmark/b22.bench
+[19/26] 任务 ./benchmark/b17.bench
+[20/26] 任务 ./benchmark/b20.bench
+[21/26] 任务 ./benchmark/c7552.bench
 [22/26] 任务 ./benchmark/b12.bench
-[23/26] 任务 ./benchmark/b21.bench
-[24/26] 任务 ./benchmark/b06.bench
-[25/26] 任务 ./benchmark/c499.bench
-[26/26] 任务 ./benchmark/c1908.bench
+[23/26] 任务 ./benchmark/c5315.bench
+[24/26] 任务 ./benchmark/b04.bench
+[25/26] 任务 ./benchmark/b07.bench
+[26/26] 任务 ./benchmark/c432.bench
diff --git a/exp_result/ATPG-LS_b01.bench.txt b/exp_result/ATPG-LS_b01.bench.txt
index 8f82a47..568cd6f 100644
--- a/exp_result/ATPG-LS_b01.bench.txt
+++ b/exp_result/ATPG-LS_b01.bench.txt
@@ -8,82 +8,85 @@ Gate:	48
 Stem:	28
 Level:	3
 ================================ 
-[SOL] flip: 0, stem: 0, fault:541. flip_cnt: 0, stem_cnt: 28, fault_cnt:42
-coverage: 43.750%	pattern: 1	before: 96	now: 54
+[SOL] flip: 0, stem: 0, fault:181. flip_cnt: 0, stem_cnt: 28, fault_cnt:41
+coverage: 42.708%	pattern: 1	before: 96	now: 55
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:145. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
-coverage: 63.542%	pattern: 2	before: 54	now: 35
+[SOL] flip: 0, stem: 0, fault:227. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
+coverage: 64.583%	pattern: 2	before: 55	now: 34
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 68.750%	pattern: 3	before: 35	now: 30
+[SOL] flip: 0, stem: 0, fault:59. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
+coverage: 77.083%	pattern: 3	before: 34	now: 22
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
-coverage: 76.042%	pattern: 4	before: 30	now: 23
+[SOL] flip: 0, stem: 0, fault:71. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
+coverage: 82.292%	pattern: 4	before: 22	now: 17
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 78.125%	pattern: 5	before: 23	now: 21
+[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
+coverage: 85.417%	pattern: 5	before: 17	now: 14
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 78.125%	pattern: 5	before: 21	now: 21
+coverage: 85.417%	pattern: 5	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:51. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
+coverage: 88.542%	pattern: 6	before: 14	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:66. flip_cnt: 0, stem_cnt: 28, fault_cnt:32
+coverage: 92.708%	pattern: 7	before: 11	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 78.125%	pattern: 5	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 78.125%	pattern: 5	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 78.125%	pattern: 5	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:75. flip_cnt: 0, stem_cnt: 28, fault_cnt:32
-coverage: 82.292%	pattern: 6	before: 21	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 82.292%	pattern: 6	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 82.292%	pattern: 6	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 82.292%	pattern: 6	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
-coverage: 82.292%	pattern: 6	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:49. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
-coverage: 86.458%	pattern: 7	before: 17	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
-coverage: 88.542%	pattern: 8	before: 13	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
-coverage: 91.667%	pattern: 9	before: 11	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
-coverage: 94.792%	pattern: 10	before: 8	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
-coverage: 95.833%	pattern: 11	before: 5	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
-coverage: 96.875%	pattern: 12	before: 4	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
-coverage: 96.875%	pattern: 12	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
-coverage: 97.917%	pattern: 13	before: 3	now: 2
+coverage: 92.708%	pattern: 7	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
-coverage: 97.917%	pattern: 13	before: 2	now: 2
+coverage: 92.708%	pattern: 7	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 28, fault_cnt:28
-coverage: 98.958%	pattern: 14	before: 2	now: 1
+[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
+coverage: 93.750%	pattern: 8	before: 7	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
-coverage: 100.000%	pattern: 15	before: 1	now: 0
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
+coverage: 95.833%	pattern: 9	before: 6	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
+coverage: 96.875%	pattern: 10	before: 4	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 28, fault_cnt:28
+coverage: 97.917%	pattern: 11	before: 3	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
+coverage: 97.917%	pattern: 11	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
+coverage: 97.917%	pattern: 11	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
+coverage: 97.917%	pattern: 11	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 28, fault_cnt:33
+coverage: 98.958%	pattern: 12	before: 2	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:24
+coverage: 98.958%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
+coverage: 98.958%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
+coverage: 98.958%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
+coverage: 98.958%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:25
+coverage: 98.958%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
+coverage: 98.958%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
+coverage: 98.958%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
+coverage: 100.000%	pattern: 13	before: 1	now: 0
 checking valid circuit ... result: 1.
 
-real	0m0.364s
-user	0m0.359s
-sys	0m0.004s
+real	0m0.239s
+user	0m0.237s
+sys	0m0.000s
diff --git a/exp_result/ATPG-LS_b02.bench.txt b/exp_result/ATPG-LS_b02.bench.txt
deleted file mode 100644
index 4385f16..0000000
--- a/exp_result/ATPG-LS_b02.bench.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-make: 'atpg' is up to date.
-========================
-parsing file ./benchmark/b02.bench ...Error while reading file: DFF is not a valid gate.
-
-real	0m0.003s
-user	0m0.001s
-sys	0m0.000s
diff --git a/exp_result/ATPG-LS_b03.bench.txt b/exp_result/ATPG-LS_b03.bench.txt
index 838fd36..57a0c0e 100644
--- a/exp_result/ATPG-LS_b03.bench.txt
+++ b/exp_result/ATPG-LS_b03.bench.txt
@@ -8,118 +8,94 @@ Gate:	152
 Stem:	86
 Level:	3
 ================================ 
-[SOL] flip: 0, stem: 0, fault:1483. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
+[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
 coverage: 38.487%	pattern: 1	before: 304	now: 187
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1222. flip_cnt: 0, stem_cnt: 86, fault_cnt:121
-coverage: 60.526%	pattern: 2	before: 187	now: 120
+[SOL] flip: 0, stem: 0, fault:440. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
+coverage: 65.789%	pattern: 2	before: 187	now: 104
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:170. flip_cnt: 0, stem_cnt: 86, fault_cnt:107
-coverage: 73.026%	pattern: 3	before: 120	now: 82
+[SOL] flip: 0, stem: 0, fault:338. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
+coverage: 78.618%	pattern: 3	before: 104	now: 65
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 86, fault_cnt:124
-coverage: 79.934%	pattern: 4	before: 82	now: 61
+[SOL] flip: 0, stem: 0, fault:113. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
+coverage: 84.539%	pattern: 4	before: 65	now: 47
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:62. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
-coverage: 83.224%	pattern: 5	before: 61	now: 51
+[SOL] flip: 0, stem: 0, fault:137. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
+coverage: 92.434%	pattern: 5	before: 47	now: 23
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:72. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
-coverage: 84.539%	pattern: 6	before: 51	now: 47
+[SOL] flip: 0, stem: 0, fault:32. flip_cnt: 0, stem_cnt: 86, fault_cnt:107
+coverage: 94.737%	pattern: 6	before: 23	now: 16
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 86, fault_cnt:121
-coverage: 85.526%	pattern: 7	before: 47	now: 44
+[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 86, fault_cnt:108
+coverage: 95.724%	pattern: 7	before: 16	now: 13
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
-coverage: 89.803%	pattern: 8	before: 44	now: 31
+[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
+coverage: 96.382%	pattern: 8	before: 13	now: 11
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:138. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
-coverage: 92.434%	pattern: 9	before: 31	now: 23
+[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
+coverage: 96.711%	pattern: 9	before: 11	now: 10
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
-coverage: 93.092%	pattern: 10	before: 23	now: 21
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
+coverage: 96.711%	pattern: 9	before: 10	now: 10
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
-coverage: 93.092%	pattern: 10	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
-coverage: 93.421%	pattern: 11	before: 21	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:127
-coverage: 93.750%	pattern: 12	before: 20	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:122
-coverage: 94.408%	pattern: 13	before: 19	now: 17
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
+coverage: 98.355%	pattern: 10	before: 10	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
-coverage: 94.408%	pattern: 13	before: 17	now: 17
+coverage: 98.355%	pattern: 10	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:86. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
-coverage: 98.355%	pattern: 14	before: 17	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
-coverage: 99.013%	pattern: 15	before: 5	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
-coverage: 99.342%	pattern: 16	before: 3	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
-coverage: 99.342%	pattern: 16	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
-coverage: 99.342%	pattern: 16	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:125
+coverage: 98.355%	pattern: 10	before: 5	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118
-coverage: 99.342%	pattern: 16	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:119
-coverage: 99.342%	pattern: 16	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
-coverage: 99.342%	pattern: 16	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:122
-coverage: 99.342%	pattern: 16	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
-coverage: 99.342%	pattern: 16	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
-coverage: 99.671%	pattern: 17	before: 2	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:121
-coverage: 99.671%	pattern: 17	before: 1	now: 1
+coverage: 98.355%	pattern: 10	before: 5	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
-coverage: 99.671%	pattern: 17	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
-coverage: 99.671%	pattern: 17	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
-coverage: 99.671%	pattern: 17	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
-coverage: 99.671%	pattern: 17	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120
-coverage: 99.671%	pattern: 17	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
-coverage: 99.671%	pattern: 17	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:113
-coverage: 99.671%	pattern: 17	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
-coverage: 99.671%	pattern: 17	before: 1	now: 1
+coverage: 98.355%	pattern: 10	before: 5	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:124
-coverage: 99.671%	pattern: 17	before: 1	now: 1
+coverage: 98.355%	pattern: 10	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:127
-coverage: 100.000%	pattern: 18	before: 1	now: 0
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:123
+coverage: 98.355%	pattern: 10	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:125
+coverage: 98.355%	pattern: 10	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118
+coverage: 98.355%	pattern: 10	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
+coverage: 99.342%	pattern: 11	before: 5	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:109
+coverage: 99.342%	pattern: 11	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:112
+coverage: 99.342%	pattern: 11	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
+coverage: 99.671%	pattern: 12	before: 2	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115
+coverage: 99.671%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
+coverage: 99.671%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116
+coverage: 99.671%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111
+coverage: 99.671%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:117
+coverage: 99.671%	pattern: 12	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 86, fault_cnt:114
+coverage: 100.000%	pattern: 13	before: 1	now: 0
 checking valid circuit ... result: 1.
 
-real	0m5.785s
-user	0m5.778s
+real	0m0.783s
+user	0m0.778s
 sys	0m0.004s
diff --git a/exp_result/ATPG-LS_b04.bench.txt b/exp_result/ATPG-LS_b04.bench.txt
index 028dbb2..1a38e7e 100644
--- a/exp_result/ATPG-LS_b04.bench.txt
+++ b/exp_result/ATPG-LS_b04.bench.txt
@@ -8,180 +8,38433 @@ Gate:	587
 Stem:	262
 Level:	7
 ================================ 
-[SOL] flip: 0, stem: 0, fault:3259. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
-coverage: 25.383%	pattern: 1	before: 1174	now: 876
+[SOL] flip: 0, stem: 0, fault:3232. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 27.172%	pattern: 1	before: 1174	now: 855
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:3249. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
-coverage: 39.949%	pattern: 2	before: 876	now: 705
+[SOL] flip: 0, stem: 0, fault:1939. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 49.233%	pattern: 2	before: 855	now: 596
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1254. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
-coverage: 45.571%	pattern: 3	before: 705	now: 639
+[SOL] flip: 0, stem: 0, fault:679. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 58.518%	pattern: 3	before: 596	now: 487
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
-coverage: 49.915%	pattern: 4	before: 639	now: 588
+[SOL] flip: 0, stem: 0, fault:1731. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 71.465%	pattern: 4	before: 487	now: 335
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:608. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
-coverage: 52.641%	pattern: 5	before: 588	now: 556
+[SOL] flip: 0, stem: 0, fault:61. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 72.061%	pattern: 5	before: 335	now: 328
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
-coverage: 53.152%	pattern: 6	before: 556	now: 550
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 72.402%	pattern: 6	before: 328	now: 324
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:874. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
-coverage: 57.070%	pattern: 7	before: 550	now: 504
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 72.487%	pattern: 7	before: 324	now: 323
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
-coverage: 57.070%	pattern: 7	before: 504	now: 504
+[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 73.169%	pattern: 8	before: 323	now: 315
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
-coverage: 57.325%	pattern: 8	before: 504	now: 501
+[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 74.446%	pattern: 9	before: 315	now: 300
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
-coverage: 57.325%	pattern: 8	before: 501	now: 501
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
-coverage: 57.325%	pattern: 8	before: 501	now: 501
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
-coverage: 57.411%	pattern: 9	before: 501	now: 500
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
-coverage: 58.433%	pattern: 10	before: 500	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
-coverage: 58.433%	pattern: 10	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
-coverage: 58.433%	pattern: 10	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
-coverage: 58.433%	pattern: 10	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
-coverage: 58.433%	pattern: 10	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
-coverage: 58.433%	pattern: 10	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
-coverage: 58.433%	pattern: 10	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
-coverage: 58.433%	pattern: 10	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
-coverage: 58.433%	pattern: 10	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
-coverage: 58.603%	pattern: 11	before: 488	now: 486
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
-coverage: 58.773%	pattern: 12	before: 486	now: 484
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
-coverage: 58.773%	pattern: 12	before: 484	now: 484
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
-coverage: 58.773%	pattern: 12	before: 484	now: 484
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
-coverage: 58.773%	pattern: 12	before: 484	now: 484
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
-coverage: 58.944%	pattern: 13	before: 484	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
-coverage: 58.944%	pattern: 13	before: 482	now: 482
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 74.446%	pattern: 9	before: 300	now: 300
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
-coverage: 58.944%	pattern: 13	before: 482	now: 482
+coverage: 74.446%	pattern: 9	before: 300	now: 300
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
-coverage: 58.944%	pattern: 13	before: 482	now: 482
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 74.446%	pattern: 9	before: 300	now: 300
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
-coverage: 58.944%	pattern: 13	before: 482	now: 482
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2152. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
-coverage: 68.995%	pattern: 14	before: 482	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
-coverage: 68.995%	pattern: 14	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
-coverage: 68.995%	pattern: 14	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
-coverage: 68.995%	pattern: 14	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:928. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
-coverage: 73.424%	pattern: 15	before: 364	now: 312
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
-coverage: 73.424%	pattern: 15	before: 312	now: 312
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
-coverage: 73.424%	pattern: 15	before: 312	now: 312
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
-coverage: 73.424%	pattern: 15	before: 312	now: 312
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
-coverage: 73.424%	pattern: 15	before: 312	now: 312
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 74.446%	pattern: 9	before: 300	now: 300
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
-coverage: 73.424%	pattern: 15	before: 312	now: 312
+coverage: 74.446%	pattern: 9	before: 300	now: 300
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:185. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 76.746%	pattern: 10	before: 300	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 76.746%	pattern: 10	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:211. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 77.768%	pattern: 11	before: 273	now: 261
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 78.790%	pattern: 12	before: 261	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 78.790%	pattern: 12	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 78.790%	pattern: 12	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 78.790%	pattern: 12	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 78.790%	pattern: 12	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 78.790%	pattern: 12	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 78.790%	pattern: 12	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 78.876%	pattern: 13	before: 249	now: 248
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 78.876%	pattern: 13	before: 248	now: 248
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 78.876%	pattern: 13	before: 248	now: 248
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 78.876%	pattern: 13	before: 248	now: 248
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 78.876%	pattern: 13	before: 248	now: 248
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 78.876%	pattern: 13	before: 248	now: 248
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 79.216%	pattern: 14	before: 248	now: 244
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:778. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 83.731%	pattern: 15	before: 244	now: 191
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 83.731%	pattern: 15	before: 191	now: 191
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1207. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 89.438%	pattern: 16	before: 191	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 89.693%	pattern: 17	before: 124	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 89.693%	pattern: 17	before: 121	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 89.693%	pattern: 17	before: 121	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 89.693%	pattern: 17	before: 121	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 89.693%	pattern: 17	before: 121	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 89.693%	pattern: 17	before: 121	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 89.693%	pattern: 17	before: 121	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 89.693%	pattern: 17	before: 121	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 89.693%	pattern: 17	before: 121	now: 121
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 89.864%	pattern: 18	before: 121	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 89.864%	pattern: 18	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 90.034%	pattern: 19	before: 119	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 90.034%	pattern: 19	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 90.034%	pattern: 19	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 90.204%	pattern: 20	before: 117	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 90.204%	pattern: 20	before: 115	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 90.204%	pattern: 20	before: 115	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 90.204%	pattern: 20	before: 115	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 90.204%	pattern: 20	before: 115	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 90.204%	pattern: 20	before: 115	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 90.290%	pattern: 21	before: 115	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 90.290%	pattern: 21	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 90.801%	pattern: 22	before: 114	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 90.801%	pattern: 22	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 90.801%	pattern: 22	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 90.801%	pattern: 22	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 90.886%	pattern: 23	before: 108	now: 107
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 90.886%	pattern: 23	before: 107	now: 107
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 92.249%	pattern: 24	before: 107	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 92.249%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:262. flip_cnt: 0, stem_cnt: 262, fault_cnt:435
+coverage: 93.697%	pattern: 25	before: 91	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 93.697%	pattern: 25	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 93.697%	pattern: 25	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 93.697%	pattern: 25	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 93.697%	pattern: 25	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 93.697%	pattern: 25	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 93.697%	pattern: 25	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 93.782%	pattern: 26	before: 74	now: 73
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 95.400%	pattern: 27	before: 73	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 95.400%	pattern: 27	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 95.400%	pattern: 27	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 95.486%	pattern: 28	before: 54	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 95.571%	pattern: 29	before: 53	now: 52
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 95.571%	pattern: 29	before: 52	now: 52
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 95.571%	pattern: 29	before: 52	now: 52
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 95.656%	pattern: 30	before: 52	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 95.656%	pattern: 30	before: 51	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 95.656%	pattern: 30	before: 51	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:433
+coverage: 95.741%	pattern: 31	before: 51	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 95.826%	pattern: 32	before: 50	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 95.826%	pattern: 32	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 96.252%	pattern: 33	before: 49	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 96.252%	pattern: 33	before: 44	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 96.422%	pattern: 34	before: 44	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 96.422%	pattern: 34	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 96.593%	pattern: 35	before: 42	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 96.593%	pattern: 35	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 96.593%	pattern: 35	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 96.593%	pattern: 35	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 96.593%	pattern: 35	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 96.593%	pattern: 35	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 96.763%	pattern: 36	before: 40	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 96.763%	pattern: 36	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 96.763%	pattern: 36	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 96.763%	pattern: 36	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 96.763%	pattern: 36	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 96.763%	pattern: 36	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 96.763%	pattern: 36	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 96.763%	pattern: 36	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 96.848%	pattern: 37	before: 38	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 96.848%	pattern: 37	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 96.848%	pattern: 37	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 96.934%	pattern: 38	before: 37	now: 36
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 97.019%	pattern: 39	before: 36	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:424
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 97.019%	pattern: 39	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 97.359%	pattern: 40	before: 35	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 97.359%	pattern: 40	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 97.700%	pattern: 41	before: 31	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 97.700%	pattern: 41	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 97.700%	pattern: 41	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 97.700%	pattern: 41	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 97.700%	pattern: 41	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 97.785%	pattern: 42	before: 27	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 97.785%	pattern: 42	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 97.871%	pattern: 43	before: 26	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 97.871%	pattern: 43	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 98.041%	pattern: 44	before: 25	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 98.041%	pattern: 44	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 98.041%	pattern: 44	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 98.041%	pattern: 44	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 98.041%	pattern: 44	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:353
+coverage: 98.041%	pattern: 44	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 98.041%	pattern: 44	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 98.041%	pattern: 44	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 98.041%	pattern: 44	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 98.211%	pattern: 45	before: 23	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 98.211%	pattern: 45	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 98.467%	pattern: 46	before: 21	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:254
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:358
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 98.467%	pattern: 46	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 98.893%	pattern: 47	before: 18	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:421
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 98.893%	pattern: 47	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 13	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:421
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:349
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:251
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:421
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:430
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:424
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:355
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:429
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:425
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:425
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:254
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:427
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:359
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:441
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:252
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:358
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:351
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:429
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:351
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:356
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:429
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:352
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:426
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:423
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:446
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:354
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:427
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:434
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:424
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:352
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:358
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:248
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:421
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:254
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:359
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:356
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:423
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:421
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:251
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:356
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:351
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:349
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:358
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:251
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.063%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.148%	pattern: 49	before: 11	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:359
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:428
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:359
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:421
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:356
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:428
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:423
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:251
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:354
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:428
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:354
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:353
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:428
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:254
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:355
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.148%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 262, fault_cnt:423
+coverage: 99.659%	pattern: 50	before: 10	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:353
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:349
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:354
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:355
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:425
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:423
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:354
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:427
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:430
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:421
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:428
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:424
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:424
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:356
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:441
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:351
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:351
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:356
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:359
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:359
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:430
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:428
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:249
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:349
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:423
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:435
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:426
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:435
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:351
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:250
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:250
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:425
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:356
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:249
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:423
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:358
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:251
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:429
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:352
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:348
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:380
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:254
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:251
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:426
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:418
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:426
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:254
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:422
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:352
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:366
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:438
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:349
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:355
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:252
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:431
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:358
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:349
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:252
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:271
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:424
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:359
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:420
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:353
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:410
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:354
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:409
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:421
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:254
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:387
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:419
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:352
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:385
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:254
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:397
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:411
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:369
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:346
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:375
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:253
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:355
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:362
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:364
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:256
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:349
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:383
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:345
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:270
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:403
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:435
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:398
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:391
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:368
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:414
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:408
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:379
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:450
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:268
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:359
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:429
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:402
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:389
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:277
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:354
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:338
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:341
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:269
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:360
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:413
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:367
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:394
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:407
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:347
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:393
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:377
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:395
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:276
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:353
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:343
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:357
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:350
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:251
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:363
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:272
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:257
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:287
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:372
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:378
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:412
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:358
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:279
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:344
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:373
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:392
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:281
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:371
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:405
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:264
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:399
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:266
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:406
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:384
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:278
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:404
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:381
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:334
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:416
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:386
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:349
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:400
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:382
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:336
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:265
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:374
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:259
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:335
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:285
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:283
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:388
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:401
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:288
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:337
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:261
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:263
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:296
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:376
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:284
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:255
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:339
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:298
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:342
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:275
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:274
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:331
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:396
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:280
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:326
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:370
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:361
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:415
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:340
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:417
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:390
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:267
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:260
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:328
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:329
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:365
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:273
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:282
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:319
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:295
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:325
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:289
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:262
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:258
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:324
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:291
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:306
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:321
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:330
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:327
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:323
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:294
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:290
+coverage: 99.659%	pattern: 50	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316
+coverage: 99.659%	pattern: 50	before: 4	now: 4
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_b06.bench.txt b/exp_result/ATPG-LS_b06.bench.txt
index cf7f372..e8ec51b 100644
--- a/exp_result/ATPG-LS_b06.bench.txt
+++ b/exp_result/ATPG-LS_b06.bench.txt
@@ -8,49 +8,67 @@ Gate:	56
 Stem:	42
 Level:	3
 ================================ 
-[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
-coverage: 39.286%	pattern: 1	before: 112	now: 68
+[SOL] flip: 0, stem: 0, fault:159. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
+coverage: 38.393%	pattern: 1	before: 112	now: 69
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:99. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
-coverage: 66.071%	pattern: 2	before: 68	now: 38
+[SOL] flip: 0, stem: 0, fault:107. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
+coverage: 65.179%	pattern: 2	before: 69	now: 39
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
-coverage: 75.000%	pattern: 3	before: 38	now: 28
+[SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
+coverage: 78.571%	pattern: 3	before: 39	now: 24
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:204. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
-coverage: 86.607%	pattern: 4	before: 28	now: 15
+[SOL] flip: 0, stem: 0, fault:64. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
+coverage: 90.179%	pattern: 4	before: 24	now: 11
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:56. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
-coverage: 90.179%	pattern: 5	before: 15	now: 11
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
+coverage: 91.071%	pattern: 5	before: 11	now: 10
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 42, fault_cnt:47
-coverage: 91.071%	pattern: 6	before: 11	now: 10
+[SOL] flip: 0, stem: 0, fault:54. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
+coverage: 94.643%	pattern: 6	before: 10	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
-coverage: 92.857%	pattern: 7	before: 10	now: 8
+[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
+coverage: 97.321%	pattern: 7	before: 6	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
-coverage: 93.750%	pattern: 8	before: 8	now: 7
+[SOL] flip: 0, stem: 0, fault:14. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
+coverage: 98.214%	pattern: 8	before: 3	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
-coverage: 96.429%	pattern: 9	before: 7	now: 4
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
+coverage: 98.214%	pattern: 8	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
-coverage: 97.321%	pattern: 10	before: 4	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
+coverage: 98.214%	pattern: 8	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
-coverage: 98.214%	pattern: 11	before: 3	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
-coverage: 99.107%	pattern: 12	before: 2	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:34
+coverage: 98.214%	pattern: 8	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
-coverage: 99.107%	pattern: 12	before: 1	now: 1
+coverage: 98.214%	pattern: 8	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
-coverage: 100.000%	pattern: 13	before: 1	now: 0
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
+coverage: 98.214%	pattern: 8	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:35
+coverage: 98.214%	pattern: 8	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
+coverage: 98.214%	pattern: 8	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
+coverage: 98.214%	pattern: 8	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 42, fault_cnt:47
+coverage: 99.107%	pattern: 9	before: 2	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
+coverage: 99.107%	pattern: 9	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
+coverage: 99.107%	pattern: 9	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
+coverage: 100.000%	pattern: 10	before: 1	now: 0
 checking valid circuit ... result: 1.
 
-real	0m0.098s
-user	0m0.093s
-sys	0m0.004s
+real	0m0.107s
+user	0m0.105s
+sys	0m0.000s
diff --git a/exp_result/ATPG-LS_b07.bench.txt b/exp_result/ATPG-LS_b07.bench.txt
index 98e8732..9755090 100644
--- a/exp_result/ATPG-LS_b07.bench.txt
+++ b/exp_result/ATPG-LS_b07.bench.txt
@@ -8,294 +8,53766 @@ Gate:	419
 Stem:	224
 Level:	5
 ================================ 
-[SOL] flip: 0, stem: 0, fault:2928. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
-coverage: 29.236%	pattern: 1	before: 838	now: 593
+[SOL] flip: 0, stem: 0, fault:2800. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 26.850%	pattern: 1	before: 838	now: 613
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2071. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
-coverage: 42.243%	pattern: 2	before: 593	now: 484
+[SOL] flip: 0, stem: 0, fault:3058. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 56.086%	pattern: 2	before: 613	now: 368
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1368. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
-coverage: 50.835%	pattern: 3	before: 484	now: 412
+[SOL] flip: 0, stem: 0, fault:2180. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 71.480%	pattern: 3	before: 368	now: 239
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
-coverage: 56.444%	pattern: 4	before: 412	now: 365
+[SOL] flip: 0, stem: 0, fault:360. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 75.418%	pattern: 4	before: 239	now: 206
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
-coverage: 57.637%	pattern: 5	before: 365	now: 355
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 76.492%	pattern: 5	before: 206	now: 197
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1767. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
-coverage: 68.735%	pattern: 6	before: 355	now: 262
+[SOL] flip: 0, stem: 0, fault:205. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 78.520%	pattern: 6	before: 197	now: 180
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
-coverage: 69.212%	pattern: 7	before: 262	now: 258
+[SOL] flip: 0, stem: 0, fault:721. flip_cnt: 0, stem_cnt: 224, fault_cnt:338
+coverage: 84.129%	pattern: 7	before: 180	now: 133
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
-coverage: 70.525%	pattern: 8	before: 258	now: 247
+[SOL] flip: 0, stem: 0, fault:260. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 86.038%	pattern: 8	before: 133	now: 117
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
-coverage: 70.525%	pattern: 8	before: 247	now: 247
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 86.158%	pattern: 9	before: 117	now: 116
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
-coverage: 70.644%	pattern: 9	before: 247	now: 246
+[SOL] flip: 0, stem: 0, fault:195. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 88.186%	pattern: 10	before: 116	now: 99
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
-coverage: 70.644%	pattern: 9	before: 246	now: 246
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 89.021%	pattern: 11	before: 99	now: 92
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
-coverage: 71.002%	pattern: 10	before: 246	now: 243
+[SOL] flip: 0, stem: 0, fault:216. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 90.811%	pattern: 12	before: 92	now: 77
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
-coverage: 71.002%	pattern: 10	before: 243	now: 243
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
-coverage: 71.241%	pattern: 11	before: 243	now: 241
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
-coverage: 71.241%	pattern: 11	before: 241	now: 241
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
-coverage: 71.241%	pattern: 11	before: 241	now: 241
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
-coverage: 71.838%	pattern: 12	before: 241	now: 236
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
-coverage: 72.673%	pattern: 13	before: 236	now: 229
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
-coverage: 72.673%	pattern: 13	before: 229	now: 229
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
-coverage: 73.628%	pattern: 14	before: 229	now: 221
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
-coverage: 79.714%	pattern: 15	before: 221	now: 170
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
-coverage: 79.714%	pattern: 15	before: 170	now: 170
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
-coverage: 80.072%	pattern: 16	before: 170	now: 167
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
-coverage: 80.072%	pattern: 16	before: 167	now: 167
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
-coverage: 80.072%	pattern: 16	before: 167	now: 167
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
-coverage: 80.072%	pattern: 16	before: 167	now: 167
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
-coverage: 80.310%	pattern: 17	before: 167	now: 165
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
-coverage: 80.310%	pattern: 17	before: 165	now: 165
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
-coverage: 80.310%	pattern: 17	before: 165	now: 165
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
-coverage: 80.310%	pattern: 17	before: 165	now: 165
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
-coverage: 80.310%	pattern: 17	before: 165	now: 165
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
-coverage: 80.310%	pattern: 17	before: 165	now: 165
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
-coverage: 80.907%	pattern: 18	before: 165	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
-coverage: 80.907%	pattern: 18	before: 160	now: 160
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:760. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
-coverage: 85.680%	pattern: 19	before: 160	now: 120
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
-coverage: 85.680%	pattern: 19	before: 120	now: 120
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
-coverage: 85.680%	pattern: 19	before: 120	now: 120
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
-coverage: 85.680%	pattern: 19	before: 120	now: 120
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
-coverage: 85.680%	pattern: 19	before: 120	now: 120
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
-coverage: 85.800%	pattern: 20	before: 120	now: 119
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
-coverage: 85.800%	pattern: 20	before: 119	now: 119
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
-coverage: 85.800%	pattern: 20	before: 119	now: 119
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
-coverage: 87.112%	pattern: 21	before: 119	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
-coverage: 87.112%	pattern: 21	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
-coverage: 87.112%	pattern: 21	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
-coverage: 87.112%	pattern: 21	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
-coverage: 87.112%	pattern: 21	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
-coverage: 87.112%	pattern: 21	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
-coverage: 87.112%	pattern: 21	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
-coverage: 87.112%	pattern: 21	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
-coverage: 87.112%	pattern: 21	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
-coverage: 87.709%	pattern: 22	before: 108	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
-coverage: 87.709%	pattern: 22	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
-coverage: 87.709%	pattern: 22	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
-coverage: 87.709%	pattern: 22	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
-coverage: 87.709%	pattern: 22	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
-coverage: 87.709%	pattern: 22	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
-coverage: 88.783%	pattern: 23	before: 103	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
-coverage: 88.783%	pattern: 23	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
-coverage: 89.737%	pattern: 24	before: 94	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
-coverage: 89.737%	pattern: 24	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
-coverage: 89.737%	pattern: 24	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
-coverage: 89.737%	pattern: 24	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
-coverage: 89.737%	pattern: 24	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
-coverage: 89.737%	pattern: 24	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
-coverage: 89.737%	pattern: 24	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
-coverage: 89.857%	pattern: 25	before: 86	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
-coverage: 89.857%	pattern: 25	before: 85	now: 85
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 91.050%	pattern: 13	before: 77	now: 75
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
-coverage: 89.857%	pattern: 25	before: 85	now: 85
+coverage: 91.050%	pattern: 13	before: 75	now: 75
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
-coverage: 89.857%	pattern: 25	before: 85	now: 85
+[SOL] flip: 0, stem: 0, fault:244. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 93.079%	pattern: 14	before: 75	now: 58
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
-coverage: 90.453%	pattern: 26	before: 85	now: 80
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 93.079%	pattern: 14	before: 58	now: 58
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
-coverage: 90.453%	pattern: 26	before: 80	now: 80
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 93.317%	pattern: 15	before: 58	now: 56
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
-coverage: 90.453%	pattern: 26	before: 80	now: 80
+[SOL] flip: 0, stem: 0, fault:58. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 93.795%	pattern: 16	before: 56	now: 52
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
-coverage: 90.453%	pattern: 26	before: 80	now: 80
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 93.795%	pattern: 16	before: 52	now: 52
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
-coverage: 90.453%	pattern: 26	before: 80	now: 80
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 94.153%	pattern: 17	before: 52	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 94.272%	pattern: 18	before: 49	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 94.272%	pattern: 18	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 94.511%	pattern: 19	before: 48	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 94.630%	pattern: 20	before: 46	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 94.630%	pattern: 20	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 94.869%	pattern: 21	before: 45	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 94.869%	pattern: 21	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 94.869%	pattern: 21	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 94.988%	pattern: 22	before: 43	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 94.988%	pattern: 22	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 94.988%	pattern: 22	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 95.107%	pattern: 23	before: 42	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 95.107%	pattern: 23	before: 41	now: 41
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
-coverage: 90.453%	pattern: 26	before: 80	now: 80
+coverage: 95.107%	pattern: 23	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 95.107%	pattern: 23	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 95.107%	pattern: 23	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:90. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.062%	pattern: 24	before: 41	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 96.062%	pattern: 24	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.181%	pattern: 25	before: 33	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.181%	pattern: 25	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.181%	pattern: 25	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 96.181%	pattern: 25	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.181%	pattern: 25	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.181%	pattern: 25	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 96.181%	pattern: 25	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 96.181%	pattern: 25	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:259
+coverage: 96.181%	pattern: 25	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.301%	pattern: 26	before: 32	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.301%	pattern: 26	before: 31	now: 31
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
-coverage: 90.453%	pattern: 26	before: 80	now: 80
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.301%	pattern: 26	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.659%	pattern: 27	before: 31	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 96.659%	pattern: 27	before: 28	now: 28
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
-coverage: 90.453%	pattern: 26	before: 80	now: 80
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.659%	pattern: 27	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.778%	pattern: 28	before: 28	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.778%	pattern: 28	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 27	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:259
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:206
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:279
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:278
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:206
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 96.897%	pattern: 29	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:79. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 97.613%	pattern: 30	before: 26	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:340
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:342
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 97.613%	pattern: 30	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 224, fault_cnt:341
+coverage: 98.091%	pattern: 31	before: 20	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:341
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:204
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:207
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:261
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:267
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:261
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:260
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.091%	pattern: 31	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 16	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:340
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:262
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:341
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:261
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:344
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:278
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:260
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:343
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:339
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:275
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:339
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:203
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:261
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.449%	pattern: 32	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 13	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:340
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:342
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:279
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:351
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:204
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:274
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:338
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:202
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.568%	pattern: 33	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 12	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:206
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:339
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:271
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:259
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:340
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:265
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:278
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:207
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:272
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:279
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:259
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:266
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:355
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:346
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:341
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:272
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:346
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:276
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:338
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:340
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:207
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:338
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:272
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:264
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:259
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:206
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:279
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:277
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:277
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:205
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:262
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:275
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:204
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:270
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:278
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:278
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:343
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:278
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:345
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:206
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:260
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:340
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:341
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:281
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:259
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:207
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:260
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:261
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:340
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:204
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:354
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:341
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:341
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:259
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:205
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:343
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:339
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:209
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:202
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:276
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:339
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:267
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:276
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:277
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:338
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:278
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:284
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:264
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:277
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:263
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:276
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:204
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:258
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:262
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:274
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:206
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:282
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:261
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:261
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:260
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:339
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:339
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:260
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:344
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:283
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:279
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:256
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:341
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:206
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:292
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:286
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:221
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:337
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:224
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:226
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:294
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:280
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:288
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:211
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:278
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:285
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:257
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:289
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:227
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:210
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:225
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:212
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:330
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:208
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:253
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:332
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:214
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:326
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:219
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:223
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:220
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:216
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:319
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:331
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:334
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:327
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:229
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:302
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:215
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:296
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:336
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:308
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:301
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:305
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:230
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:290
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:312
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:328
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:318
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:333
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:313
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:287
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:298
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:315
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:329
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:303
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:335
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:251
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:297
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:213
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:317
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:306
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:300
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:316
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:309
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:293
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:299
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:310
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:311
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:222
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:307
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:325
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:322
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:304
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:321
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:320
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:291
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:323
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:314
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:295
+coverage: 98.687%	pattern: 34	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239
+coverage: 98.687%	pattern: 34	before: 11	now: 11
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_b08.bench.txt b/exp_result/ATPG-LS_b08.bench.txt
index 67c865b..6bf6393 100644
--- a/exp_result/ATPG-LS_b08.bench.txt
+++ b/exp_result/ATPG-LS_b08.bench.txt
@@ -8,6127 +8,3646 @@ Gate:	167
 Stem:	98
 Level:	3
 ================================ 
-[SOL] flip: 0, stem: 0, fault:417. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 30.838%	pattern: 1	before: 334	now: 231
+[SOL] flip: 0, stem: 0, fault:408. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 31.437%	pattern: 1	before: 334	now: 229
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:517. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 54.491%	pattern: 2	before: 231	now: 152
+[SOL] flip: 0, stem: 0, fault:595. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 54.491%	pattern: 2	before: 229	now: 152
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 60.778%	pattern: 3	before: 152	now: 131
+[SOL] flip: 0, stem: 0, fault:698. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 67.964%	pattern: 3	before: 152	now: 107
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 67.365%	pattern: 4	before: 131	now: 109
+[SOL] flip: 0, stem: 0, fault:90. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 70.060%	pattern: 4	before: 107	now: 100
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:554. flip_cnt: 0, stem_cnt: 98, fault_cnt:117
-coverage: 76.946%	pattern: 5	before: 109	now: 77
+[SOL] flip: 0, stem: 0, fault:148. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 76.347%	pattern: 5	before: 100	now: 79
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 79.940%	pattern: 6	before: 77	now: 67
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 78.443%	pattern: 6	before: 79	now: 72
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 79.940%	pattern: 6	before: 67	now: 67
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 81.138%	pattern: 7	before: 72	now: 63
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 79.940%	pattern: 6	before: 67	now: 67
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 81.138%	pattern: 7	before: 63	now: 63
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 80.240%	pattern: 7	before: 67	now: 66
+[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 82.036%	pattern: 8	before: 63	now: 60
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 81.737%	pattern: 8	before: 66	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 81.737%	pattern: 8	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 81.737%	pattern: 8	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 81.737%	pattern: 8	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 84.132%	pattern: 9	before: 61	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 84.132%	pattern: 9	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 85.928%	pattern: 10	before: 53	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 86.826%	pattern: 11	before: 47	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 87.126%	pattern: 12	before: 44	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:30. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 88.024%	pattern: 13	before: 43	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 88.024%	pattern: 13	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
-coverage: 88.922%	pattern: 14	before: 40	now: 37
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 88.922%	pattern: 14	before: 37	now: 37
+[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 82.635%	pattern: 9	before: 60	now: 58
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 88.922%	pattern: 14	before: 37	now: 37
+coverage: 82.635%	pattern: 9	before: 58	now: 58
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 98, fault_cnt:128
-coverage: 91.317%	pattern: 15	before: 37	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 91.317%	pattern: 15	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 91.317%	pattern: 15	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 91.317%	pattern: 15	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 91.317%	pattern: 15	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 91.317%	pattern: 15	before: 29	now: 29
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 83.533%	pattern: 10	before: 58	now: 55
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 91.317%	pattern: 15	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 91.617%	pattern: 16	before: 29	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 91.617%	pattern: 16	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 91.617%	pattern: 16	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 91.916%	pattern: 17	before: 28	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 91.916%	pattern: 17	before: 27	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 92.515%	pattern: 18	before: 27	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 92.515%	pattern: 18	before: 25	now: 25
+coverage: 83.533%	pattern: 10	before: 55	now: 55
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 92.515%	pattern: 18	before: 25	now: 25
+coverage: 83.533%	pattern: 10	before: 55	now: 55
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 92.515%	pattern: 18	before: 25	now: 25
+coverage: 83.533%	pattern: 10	before: 55	now: 55
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 92.515%	pattern: 18	before: 25	now: 25
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 98, fault_cnt:117
+coverage: 86.826%	pattern: 11	before: 55	now: 44
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 92.515%	pattern: 18	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 94.311%	pattern: 19	before: 25	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 94.311%	pattern: 19	before: 19	now: 19
+coverage: 86.826%	pattern: 11	before: 44	now: 44
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 94.311%	pattern: 19	before: 19	now: 19
+coverage: 86.826%	pattern: 11	before: 44	now: 44
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 94.311%	pattern: 19	before: 19	now: 19
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 87.425%	pattern: 12	before: 44	now: 42
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 94.311%	pattern: 19	before: 19	now: 19
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 88.623%	pattern: 13	before: 42	now: 38
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 94.311%	pattern: 19	before: 19	now: 19
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 89.222%	pattern: 14	before: 38	now: 36
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 94.311%	pattern: 19	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 94.611%	pattern: 20	before: 19	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 94.611%	pattern: 20	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:36. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 95.210%	pattern: 21	before: 18	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 95.210%	pattern: 21	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 95.509%	pattern: 22	before: 16	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 95.509%	pattern: 22	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 98, fault_cnt:128
-coverage: 95.808%	pattern: 23	before: 15	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 96.407%	pattern: 24	before: 14	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 96.707%	pattern: 25	before: 12	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 96.707%	pattern: 25	before: 11	now: 11
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 90.120%	pattern: 15	before: 36	now: 33
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 96.707%	pattern: 25	before: 11	now: 11
+coverage: 90.120%	pattern: 15	before: 33	now: 33
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:133
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 96.707%	pattern: 25	before: 11	now: 11
+[SOL] flip: 0, stem: 0, fault:27. flip_cnt: 0, stem_cnt: 98, fault_cnt:134
+coverage: 92.515%	pattern: 16	before: 33	now: 25
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 96.707%	pattern: 25	before: 11	now: 11
+coverage: 92.515%	pattern: 16	before: 25	now: 25
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 96.707%	pattern: 25	before: 11	now: 11
+[SOL] flip: 0, stem: 0, fault:32. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 93.114%	pattern: 17	before: 25	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 93.413%	pattern: 18	before: 23	now: 22
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 96.707%	pattern: 25	before: 11	now: 11
+coverage: 93.413%	pattern: 18	before: 22	now: 22
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 96.707%	pattern: 25	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 96.707%	pattern: 25	before: 11	now: 11
+coverage: 93.413%	pattern: 18	before: 22	now: 22
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 96.707%	pattern: 25	before: 11	now: 11
+coverage: 93.413%	pattern: 18	before: 22	now: 22
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 97.006%	pattern: 26	before: 11	now: 10
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 93.413%	pattern: 18	before: 22	now: 22
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 97.006%	pattern: 26	before: 10	now: 10
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 93.413%	pattern: 18	before: 22	now: 22
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
-coverage: 97.006%	pattern: 26	before: 10	now: 10
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 93.413%	pattern: 18	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 93.413%	pattern: 18	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 94.012%	pattern: 19	before: 22	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 94.012%	pattern: 19	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 94.012%	pattern: 19	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 94.012%	pattern: 19	before: 20	now: 20
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 94.311%	pattern: 20	before: 20	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 94.311%	pattern: 20	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 94.311%	pattern: 20	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 94.910%	pattern: 21	before: 19	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 94.910%	pattern: 21	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 95.210%	pattern: 22	before: 17	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 95.210%	pattern: 22	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:14. flip_cnt: 0, stem_cnt: 98, fault_cnt:126
+coverage: 95.808%	pattern: 23	before: 16	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 95.808%	pattern: 23	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 95.808%	pattern: 23	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 95.808%	pattern: 23	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 98, fault_cnt:122
+coverage: 96.407%	pattern: 24	before: 14	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 96.407%	pattern: 24	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 96.707%	pattern: 25	before: 12	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 96.707%	pattern: 25	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 98, fault_cnt:119
+coverage: 97.006%	pattern: 26	before: 11	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 97.006%	pattern: 26	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 97.006%	pattern: 26	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 97.006%	pattern: 26	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 97.006%	pattern: 26	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 97.006%	pattern: 26	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 97.006%	pattern: 26	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
 coverage: 97.305%	pattern: 27	before: 10	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 97.305%	pattern: 27	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 97.305%	pattern: 27	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 97.305%	pattern: 27	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 97.305%	pattern: 27	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 97.305%	pattern: 27	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 97.305%	pattern: 27	before: 9	now: 9
-checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 97.305%	pattern: 27	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 97.305%	pattern: 27	before: 9	now: 9
-checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 97.305%	pattern: 27	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:82
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
 coverage: 97.305%	pattern: 27	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
 coverage: 97.605%	pattern: 28	before: 9	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 97.605%	pattern: 28	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 97.605%	pattern: 28	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 97.605%	pattern: 28	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 97.605%	pattern: 28	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
 coverage: 97.605%	pattern: 28	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
 coverage: 97.605%	pattern: 28	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
 coverage: 97.605%	pattern: 28	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
 coverage: 97.605%	pattern: 28	before: 8	now: 8
 checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 97.605%	pattern: 28	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 97.904%	pattern: 29	before: 8	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 97.904%	pattern: 29	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 97.904%	pattern: 29	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 97.904%	pattern: 29	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 97.904%	pattern: 29	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 97.904%	pattern: 29	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 97.904%	pattern: 29	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 98.204%	pattern: 30	before: 7	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 98.204%	pattern: 30	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 98.503%	pattern: 31	before: 6	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 98.503%	pattern: 31	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 98.802%	pattern: 32	before: 5	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 98.802%	pattern: 32	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 98.802%	pattern: 32	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 98.802%	pattern: 32	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 98.802%	pattern: 32	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 98.802%	pattern: 32	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 98.802%	pattern: 32	before: 4	now: 4
+checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 97.605%	pattern: 28	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 97.605%	pattern: 28	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 97.605%	pattern: 28	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 98, fault_cnt:121
-coverage: 98.204%	pattern: 29	before: 8	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.204%	pattern: 29	before: 6	now: 6
+coverage: 98.802%	pattern: 32	before: 4	now: 4
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 98.204%	pattern: 29	before: 6	now: 6
+coverage: 98.802%	pattern: 32	before: 4	now: 4
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.204%	pattern: 29	before: 6	now: 6
+coverage: 98.802%	pattern: 32	before: 4	now: 4
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.204%	pattern: 29	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 98, fault_cnt:126
-coverage: 98.802%	pattern: 30	before: 6	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 98.802%	pattern: 30	before: 4	now: 4
+coverage: 98.802%	pattern: 32	before: 4	now: 4
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.802%	pattern: 30	before: 4	now: 4
+coverage: 98.802%	pattern: 32	before: 4	now: 4
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:131
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.802%	pattern: 30	before: 4	now: 4
+coverage: 98.802%	pattern: 32	before: 4	now: 4
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 98.802%	pattern: 30	before: 4	now: 4
+coverage: 98.802%	pattern: 32	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 98.802%	pattern: 30	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.102%	pattern: 33	before: 4	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 98.802%	pattern: 30	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 3	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 98.802%	pattern: 30	before: 4	now: 4
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 98.802%	pattern: 30	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.102%	pattern: 31	before: 4	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:78
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.102%	pattern: 31	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:124
-coverage: 99.401%	pattern: 32	before: 3	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:127
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:117
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:118
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:121
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:82
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:129
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:134
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:80
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:126
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:120
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:118
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.401%	pattern: 32	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:117
-coverage: 99.401%	pattern: 32	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.701%	pattern: 33	before: 2	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:118
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:120
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:124
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
-coverage: 99.701%	pattern: 33	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:127
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:124
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:125
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
-coverage: 99.701%	pattern: 33	before: 1	now: 1
+coverage: 99.401%	pattern: 34	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
-coverage: 100.000%	pattern: 34	before: 1	now: 0
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:132
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.401%	pattern: 34	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 2	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:122
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:119
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:118
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:126
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:124
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103
+coverage: 99.701%	pattern: 35	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 98, fault_cnt:132
+coverage: 100.000%	pattern: 36	before: 1	now: 0
 checking valid circuit ... result: 1.
 
-real	2m38.563s
-user	2m38.546s
+real	0m44.872s
+user	0m44.860s
 sys	0m0.004s
diff --git a/exp_result/ATPG-LS_b09.bench.txt b/exp_result/ATPG-LS_b09.bench.txt
index 2a3cdca..dcc2144 100644
--- a/exp_result/ATPG-LS_b09.bench.txt
+++ b/exp_result/ATPG-LS_b09.bench.txt
@@ -8,1288 +8,139 @@ Gate:	142
 Stem:	79
 Level:	3
 ================================ 
-[SOL] flip: 0, stem: 0, fault:267. flip_cnt: 0, stem_cnt: 79, fault_cnt:121
-coverage: 42.606%	pattern: 1	before: 284	now: 163
+[SOL] flip: 0, stem: 0, fault:606. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+coverage: 39.789%	pattern: 1	before: 284	now: 171
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:678. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 72.535%	pattern: 2	before: 163	now: 78
+[SOL] flip: 0, stem: 0, fault:402. flip_cnt: 0, stem_cnt: 79, fault_cnt:91
+coverage: 64.437%	pattern: 2	before: 171	now: 101
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 79.930%	pattern: 3	before: 78	now: 57
+[SOL] flip: 0, stem: 0, fault:142. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+coverage: 70.775%	pattern: 3	before: 101	now: 83
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:195. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 83.803%	pattern: 4	before: 57	now: 46
+[SOL] flip: 0, stem: 0, fault:150. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+coverage: 79.930%	pattern: 4	before: 83	now: 57
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:45. flip_cnt: 0, stem_cnt: 79, fault_cnt:83
-coverage: 90.493%	pattern: 5	before: 46	now: 27
+[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 89.085%	pattern: 5	before: 57	now: 31
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 91.549%	pattern: 6	before: 27	now: 24
+[SOL] flip: 0, stem: 0, fault:154. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+coverage: 93.310%	pattern: 6	before: 31	now: 19
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 92.958%	pattern: 7	before: 24	now: 20
+[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+coverage: 93.662%	pattern: 7	before: 19	now: 18
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 92.958%	pattern: 7	before: 20	now: 20
+[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 94.014%	pattern: 8	before: 18	now: 17
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:29. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
-coverage: 95.070%	pattern: 8	before: 20	now: 14
+[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+coverage: 94.366%	pattern: 9	before: 17	now: 16
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 95.423%	pattern: 9	before: 14	now: 13
+[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
+coverage: 94.718%	pattern: 10	before: 16	now: 15
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 95.423%	pattern: 9	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
-coverage: 96.127%	pattern: 10	before: 13	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
-coverage: 96.127%	pattern: 10	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 96.127%	pattern: 10	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 96.127%	pattern: 10	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 96.127%	pattern: 10	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 96.127%	pattern: 10	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 96.479%	pattern: 11	before: 11	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 96.479%	pattern: 11	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 96.479%	pattern: 11	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 96.479%	pattern: 11	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 96.479%	pattern: 11	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 96.479%	pattern: 11	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 96.479%	pattern: 11	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 96.831%	pattern: 12	before: 10	now: 9
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+coverage: 95.070%	pattern: 11	before: 15	now: 14
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 96.831%	pattern: 12	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 96.831%	pattern: 12	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 96.831%	pattern: 12	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 96.831%	pattern: 12	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 96.831%	pattern: 12	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 96.831%	pattern: 12	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 9	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 95.070%	pattern: 11	before: 14	now: 14
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 95.070%	pattern: 11	before: 14	now: 14
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 95.070%	pattern: 11	before: 14	now: 14
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
+coverage: 95.423%	pattern: 12	before: 14	now: 13
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 79, fault_cnt:83
+coverage: 97.535%	pattern: 13	before: 13	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 97.535%	pattern: 13	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:101
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 97.535%	pattern: 13	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 97.535%	pattern: 13	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 97.535%	pattern: 13	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:95
+coverage: 97.887%	pattern: 14	before: 7	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
+coverage: 97.887%	pattern: 14	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 97.887%	pattern: 14	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 97.887%	pattern: 14	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
+coverage: 97.887%	pattern: 14	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.183%	pattern: 13	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 97.887%	pattern: 14	before: 8	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
 coverage: 97.887%	pattern: 14	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 97.887%	pattern: 14	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 79, fault_cnt:83
+[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
 coverage: 98.239%	pattern: 15	before: 6	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
 coverage: 98.239%	pattern: 15	before: 5	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
 coverage: 98.239%	pattern: 15	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:101
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:78
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.239%	pattern: 15	before: 5	now: 5
-checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
 coverage: 98.239%	pattern: 15	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 79, fault_cnt:97
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 79, fault_cnt:91
 coverage: 98.592%	pattern: 16	before: 5	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:94
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:99
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 98.592%	pattern: 16	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
@@ -1298,391 +149,70 @@ checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:92
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:92
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:76
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
 coverage: 98.592%	pattern: 16	before: 4	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.592%	pattern: 16	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:94
+[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
 coverage: 98.944%	pattern: 17	before: 4	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:101
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 98.944%	pattern: 17	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 79, fault_cnt:94
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:95
 coverage: 99.296%	pattern: 18	before: 3	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
@@ -1691,25 +221,34 @@ checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:76
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
+coverage: 99.296%	pattern: 18	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
@@ -1718,331 +257,115 @@ checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:101
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:92
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
 coverage: 99.296%	pattern: 18	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.296%	pattern: 18	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:95
+[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 79, fault_cnt:97
 coverage: 99.648%	pattern: 19	before: 2	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:97
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:94
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:76
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
@@ -2051,190 +374,319 @@ checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:92
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:78
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:80
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:80
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86
+coverage: 99.648%	pattern: 19	before: 1	now: 1
+checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:83
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85
 coverage: 99.648%	pattern: 19	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:120
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:88
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:120
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111
-coverage: 99.648%	pattern: 19	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 79, fault_cnt:92
+[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 79, fault_cnt:94
 coverage: 100.000%	pattern: 20	before: 1	now: 0
 checking valid circuit ... result: 1.
 
-real	1m21.293s
-user	1m21.286s
+real	0m6.723s
+user	0m6.720s
 sys	0m0.000s
diff --git a/exp_result/ATPG-LS_b10.bench.txt b/exp_result/ATPG-LS_b10.bench.txt
index 0b54168..1300a80 100644
--- a/exp_result/ATPG-LS_b10.bench.txt
+++ b/exp_result/ATPG-LS_b10.bench.txt
@@ -8,424 +8,934 @@ Gate:	182
 Stem:	91
 Level:	3
 ================================ 
-[SOL] flip: 0, stem: 0, fault:1187. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
-coverage: 30.495%	pattern: 1	before: 364	now: 253
+[SOL] flip: 0, stem: 0, fault:1035. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
+coverage: 30.769%	pattern: 1	before: 364	now: 252
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:779. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
-coverage: 41.758%	pattern: 2	before: 253	now: 212
+[SOL] flip: 0, stem: 0, fault:665. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 45.879%	pattern: 2	before: 252	now: 197
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:792. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 53.297%	pattern: 3	before: 212	now: 170
+[SOL] flip: 0, stem: 0, fault:387. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 56.044%	pattern: 3	before: 197	now: 160
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:453. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 67.308%	pattern: 4	before: 170	now: 119
+[SOL] flip: 0, stem: 0, fault:253. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 60.440%	pattern: 4	before: 160	now: 144
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 68.407%	pattern: 5	before: 119	now: 115
+[SOL] flip: 0, stem: 0, fault:70. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 62.637%	pattern: 5	before: 144	now: 136
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
-coverage: 68.956%	pattern: 6	before: 115	now: 113
+[SOL] flip: 0, stem: 0, fault:203. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
+coverage: 70.055%	pattern: 6	before: 136	now: 109
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
-coverage: 74.176%	pattern: 7	before: 113	now: 94
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 70.879%	pattern: 7	before: 109	now: 106
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 76.923%	pattern: 8	before: 94	now: 84
+[SOL] flip: 0, stem: 0, fault:256. flip_cnt: 0, stem_cnt: 91, fault_cnt:120
+coverage: 76.923%	pattern: 8	before: 106	now: 84
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 77.473%	pattern: 9	before: 84	now: 82
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 78.022%	pattern: 9	before: 84	now: 80
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:135. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
-coverage: 79.945%	pattern: 10	before: 82	now: 73
+[SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 78.571%	pattern: 10	before: 80	now: 78
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:115. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 80.495%	pattern: 11	before: 78	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:147. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
+coverage: 85.165%	pattern: 12	before: 71	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 85.989%	pattern: 13	before: 54	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:54. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 90.659%	pattern: 14	before: 51	now: 34
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
-coverage: 79.945%	pattern: 10	before: 73	now: 73
+coverage: 90.659%	pattern: 14	before: 34	now: 34
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 81.044%	pattern: 11	before: 73	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
-coverage: 82.692%	pattern: 12	before: 69	now: 63
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
-coverage: 83.242%	pattern: 13	before: 63	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
-coverage: 84.066%	pattern: 14	before: 61	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
-coverage: 84.066%	pattern: 14	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 85.440%	pattern: 15	before: 58	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
-coverage: 85.440%	pattern: 15	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
-coverage: 85.989%	pattern: 16	before: 53	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 85.989%	pattern: 16	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 85.989%	pattern: 16	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
-coverage: 89.011%	pattern: 17	before: 51	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
-coverage: 89.286%	pattern: 18	before: 40	now: 39
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
-coverage: 89.560%	pattern: 19	before: 39	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
-coverage: 89.560%	pattern: 19	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
-coverage: 89.560%	pattern: 19	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:120
-coverage: 89.560%	pattern: 19	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
-coverage: 89.560%	pattern: 19	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
-coverage: 90.110%	pattern: 20	before: 38	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
-coverage: 90.110%	pattern: 20	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
-coverage: 90.110%	pattern: 20	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 90.110%	pattern: 20	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
-coverage: 90.110%	pattern: 20	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 91.209%	pattern: 21	before: 36	now: 32
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
-coverage: 91.209%	pattern: 21	before: 32	now: 32
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 92.033%	pattern: 22	before: 32	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
-coverage: 92.033%	pattern: 22	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
-coverage: 92.033%	pattern: 22	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 92.033%	pattern: 22	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
-coverage: 92.033%	pattern: 22	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 93.407%	pattern: 23	before: 29	now: 24
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
-coverage: 93.407%	pattern: 23	before: 24	now: 24
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:85
-coverage: 93.407%	pattern: 23	before: 24	now: 24
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
-coverage: 93.407%	pattern: 23	before: 24	now: 24
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
-coverage: 93.407%	pattern: 23	before: 24	now: 24
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 93.956%	pattern: 24	before: 24	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
-coverage: 93.956%	pattern: 24	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
-coverage: 93.956%	pattern: 24	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 93.956%	pattern: 24	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
-coverage: 93.956%	pattern: 24	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 93.956%	pattern: 24	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 93.956%	pattern: 24	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 93.956%	pattern: 24	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
-coverage: 94.505%	pattern: 25	before: 22	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 95.604%	pattern: 26	before: 20	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
-coverage: 95.604%	pattern: 26	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 95.604%	pattern: 26	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
-coverage: 95.604%	pattern: 26	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
-coverage: 95.604%	pattern: 26	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 95.604%	pattern: 26	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 95.604%	pattern: 26	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
-coverage: 95.604%	pattern: 26	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
-coverage: 95.879%	pattern: 27	before: 16	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
-coverage: 95.879%	pattern: 27	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
-coverage: 96.429%	pattern: 28	before: 15	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
-coverage: 96.429%	pattern: 28	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
-coverage: 96.429%	pattern: 28	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 96.429%	pattern: 28	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:89
-coverage: 96.429%	pattern: 28	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
-coverage: 96.429%	pattern: 28	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
-coverage: 96.429%	pattern: 28	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 96.429%	pattern: 28	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 96.703%	pattern: 29	before: 13	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 96.703%	pattern: 29	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
-coverage: 96.703%	pattern: 29	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:59. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
-coverage: 98.077%	pattern: 30	before: 12	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
-coverage: 98.626%	pattern: 31	before: 7	now: 5
+[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 91.209%	pattern: 15	before: 34	now: 32
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
-coverage: 98.626%	pattern: 31	before: 5	now: 5
+coverage: 91.209%	pattern: 15	before: 32	now: 32
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
-coverage: 98.626%	pattern: 31	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
+coverage: 92.308%	pattern: 16	before: 32	now: 28
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
-coverage: 98.626%	pattern: 31	before: 5	now: 5
+coverage: 92.308%	pattern: 16	before: 28	now: 28
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
-coverage: 98.626%	pattern: 31	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
+coverage: 92.857%	pattern: 17	before: 28	now: 26
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 98.626%	pattern: 31	before: 5	now: 5
+coverage: 92.857%	pattern: 17	before: 26	now: 26
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 98.626%	pattern: 31	before: 5	now: 5
+coverage: 92.857%	pattern: 17	before: 26	now: 26
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
-coverage: 98.626%	pattern: 31	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
-coverage: 98.901%	pattern: 32	before: 5	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 93.132%	pattern: 18	before: 26	now: 25
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+coverage: 93.132%	pattern: 18	before: 25	now: 25
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:93
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 93.132%	pattern: 18	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:31. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
+coverage: 93.956%	pattern: 19	before: 25	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 94.231%	pattern: 20	before: 22	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:90
+coverage: 94.231%	pattern: 20	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:32. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 94.780%	pattern: 21	before: 21	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 94.780%	pattern: 21	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 94.780%	pattern: 21	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:41. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 95.604%	pattern: 22	before: 19	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
+coverage: 95.879%	pattern: 23	before: 16	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:29. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
+coverage: 96.429%	pattern: 24	before: 15	now: 13
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+coverage: 96.429%	pattern: 24	before: 13	now: 13
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+coverage: 96.429%	pattern: 24	before: 13	now: 13
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91
-coverage: 98.901%	pattern: 32	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
+coverage: 96.429%	pattern: 24	before: 13	now: 13
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+coverage: 96.429%	pattern: 24	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
+coverage: 97.527%	pattern: 25	before: 13	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 97.802%	pattern: 26	before: 9	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 97.802%	pattern: 26	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
+coverage: 97.802%	pattern: 26	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+coverage: 97.802%	pattern: 26	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 98.077%	pattern: 27	before: 8	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 98.626%	pattern: 28	before: 7	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:35. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.451%	pattern: 29	before: 5	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
+coverage: 99.451%	pattern: 29	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
-coverage: 98.901%	pattern: 32	before: 4	now: 4
+coverage: 99.451%	pattern: 29	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:51. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
-coverage: 100.000%	pattern: 33	before: 4	now: 0
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.451%	pattern: 29	before: 2	now: 2
 checking valid circuit ... result: 1.
-    
-real	0m36.403s
-user	0m36.398s
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:119
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.451%	pattern: 29	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
+coverage: 99.725%	pattern: 30	before: 2	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:93
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:84
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:92
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:120
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:117
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:115
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:116
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104
+coverage: 99.725%	pattern: 30	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:118
+coverage: 100.000%	pattern: 31	before: 1	now: 0
+checking valid circuit ... result: 1.
+
+real	0m13.802s
+user	0m13.797s
 sys	0m0.000s
diff --git a/exp_result/ATPG-LS_b11.bench.txt b/exp_result/ATPG-LS_b11.bench.txt
index e644aaf..9a2b8b3 100644
--- a/exp_result/ATPG-LS_b11.bench.txt
+++ b/exp_result/ATPG-LS_b11.bench.txt
@@ -8,1290 +8,24264 @@ Gate:	429
 Stem:	214
 Level:	5
 ================================ 
-[SOL] flip: 0, stem: 0, fault:3640. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
-coverage: 23.776%	pattern: 1	before: 858	now: 654
+[SOL] flip: 0, stem: 0, fault:2276. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 20.396%	pattern: 1	before: 858	now: 683
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1805. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 34.848%	pattern: 2	before: 654	now: 559
+[SOL] flip: 0, stem: 0, fault:3660. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 43.240%	pattern: 2	before: 683	now: 487
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 39.394%	pattern: 3	before: 559	now: 520
+[SOL] flip: 0, stem: 0, fault:1080. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 51.049%	pattern: 3	before: 487	now: 420
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:531. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 42.657%	pattern: 4	before: 520	now: 492
+[SOL] flip: 0, stem: 0, fault:706. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 56.410%	pattern: 4	before: 420	now: 374
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2148. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
-coverage: 55.944%	pattern: 5	before: 492	now: 378
+[SOL] flip: 0, stem: 0, fault:118. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 57.576%	pattern: 5	before: 374	now: 364
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 57.459%	pattern: 6	before: 378	now: 365
+[SOL] flip: 0, stem: 0, fault:479. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 60.606%	pattern: 6	before: 364	now: 338
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1472. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
-coverage: 66.550%	pattern: 7	before: 365	now: 287
+[SOL] flip: 0, stem: 0, fault:473. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 63.520%	pattern: 7	before: 338	now: 313
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 66.783%	pattern: 8	before: 287	now: 285
+[SOL] flip: 0, stem: 0, fault:873. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 69.114%	pattern: 8	before: 313	now: 265
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 68.065%	pattern: 9	before: 285	now: 274
+[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 71.562%	pattern: 9	before: 265	now: 244
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
-coverage: 69.930%	pattern: 10	before: 274	now: 258
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 72.261%	pattern: 10	before: 244	now: 238
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 70.396%	pattern: 11	before: 258	now: 254
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 70.979%	pattern: 12	before: 254	now: 249
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 71.212%	pattern: 13	before: 249	now: 247
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 71.212%	pattern: 13	before: 247	now: 247
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 72.611%	pattern: 11	before: 238	now: 235
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 71.329%	pattern: 14	before: 247	now: 246
+coverage: 72.727%	pattern: 12	before: 235	now: 234
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
-coverage: 71.445%	pattern: 15	before: 246	now: 245
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
-coverage: 71.678%	pattern: 16	before: 245	now: 243
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:779. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
-coverage: 76.457%	pattern: 17	before: 243	now: 202
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
-coverage: 76.457%	pattern: 17	before: 202	now: 202
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 76.457%	pattern: 17	before: 202	now: 202
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 76.457%	pattern: 17	before: 202	now: 202
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
-coverage: 77.622%	pattern: 18	before: 202	now: 192
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
-coverage: 77.739%	pattern: 19	before: 192	now: 191
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
-coverage: 78.205%	pattern: 20	before: 191	now: 187
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
-coverage: 78.322%	pattern: 21	before: 187	now: 186
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
-coverage: 78.322%	pattern: 21	before: 186	now: 186
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
-coverage: 78.555%	pattern: 22	before: 186	now: 184
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
-coverage: 78.555%	pattern: 22	before: 184	now: 184
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 78.671%	pattern: 23	before: 184	now: 183
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 78.671%	pattern: 23	before: 183	now: 183
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
-coverage: 78.671%	pattern: 23	before: 183	now: 183
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:722. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
-coverage: 83.100%	pattern: 24	before: 183	now: 145
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 83.100%	pattern: 24	before: 145	now: 145
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 83.100%	pattern: 24	before: 145	now: 145
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 83.100%	pattern: 24	before: 145	now: 145
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
-coverage: 83.100%	pattern: 24	before: 145	now: 145
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 83.100%	pattern: 24	before: 145	now: 145
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 83.100%	pattern: 24	before: 145	now: 145
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 214, fault_cnt:222
-coverage: 84.382%	pattern: 25	before: 145	now: 134
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
-coverage: 84.499%	pattern: 26	before: 134	now: 133
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
-coverage: 84.499%	pattern: 26	before: 133	now: 133
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
-coverage: 84.499%	pattern: 26	before: 133	now: 133
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 84.499%	pattern: 26	before: 133	now: 133
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 84.499%	pattern: 26	before: 133	now: 133
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
-coverage: 84.499%	pattern: 26	before: 133	now: 133
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 84.499%	pattern: 26	before: 133	now: 133
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 84.732%	pattern: 27	before: 133	now: 131
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 84.732%	pattern: 27	before: 131	now: 131
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
-coverage: 84.732%	pattern: 27	before: 131	now: 131
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 84.732%	pattern: 27	before: 131	now: 131
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 84.732%	pattern: 27	before: 131	now: 131
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
-coverage: 84.732%	pattern: 27	before: 131	now: 131
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 84.732%	pattern: 27	before: 131	now: 131
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 84.732%	pattern: 27	before: 131	now: 131
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 85.664%	pattern: 28	before: 131	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 85.664%	pattern: 28	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 85.664%	pattern: 28	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 85.664%	pattern: 28	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 85.664%	pattern: 28	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 85.664%	pattern: 28	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 85.664%	pattern: 28	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
-coverage: 85.781%	pattern: 29	before: 123	now: 122
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
-coverage: 88.228%	pattern: 30	before: 122	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 88.228%	pattern: 30	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 88.345%	pattern: 31	before: 101	now: 100
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
-coverage: 88.345%	pattern: 31	before: 100	now: 100
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 88.345%	pattern: 31	before: 100	now: 100
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
-coverage: 88.345%	pattern: 31	before: 100	now: 100
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
-coverage: 88.345%	pattern: 31	before: 100	now: 100
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
-coverage: 89.744%	pattern: 32	before: 100	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 89.744%	pattern: 32	before: 88	now: 88
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
-coverage: 90.210%	pattern: 33	before: 88	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 90.210%	pattern: 33	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 90.210%	pattern: 33	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
-coverage: 90.210%	pattern: 33	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 90.210%	pattern: 33	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
-coverage: 90.676%	pattern: 34	before: 84	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 90.676%	pattern: 34	before: 80	now: 80
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
-coverage: 90.909%	pattern: 35	before: 80	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 90.909%	pattern: 35	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
-coverage: 91.259%	pattern: 36	before: 78	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 91.259%	pattern: 36	before: 75	now: 75
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 73.077%	pattern: 13	before: 234	now: 231
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 91.259%	pattern: 36	before: 75	now: 75
+coverage: 73.077%	pattern: 13	before: 231	now: 231
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 91.259%	pattern: 36	before: 75	now: 75
+coverage: 73.077%	pattern: 13	before: 231	now: 231
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 91.259%	pattern: 36	before: 75	now: 75
+[SOL] flip: 0, stem: 0, fault:813. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 79.604%	pattern: 14	before: 231	now: 175
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 91.259%	pattern: 36	before: 75	now: 75
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 79.720%	pattern: 15	before: 175	now: 174
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 91.259%	pattern: 36	before: 75	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
-coverage: 92.191%	pattern: 37	before: 75	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 92.191%	pattern: 37	before: 67	now: 67
+[SOL] flip: 0, stem: 0, fault:273. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 81.702%	pattern: 16	before: 174	now: 157
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 92.191%	pattern: 37	before: 67	now: 67
+coverage: 81.702%	pattern: 16	before: 157	now: 157
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:207
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
-coverage: 92.191%	pattern: 37	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 92.191%	pattern: 37	before: 67	now: 67
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 81.818%	pattern: 17	before: 157	now: 156
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 92.191%	pattern: 37	before: 67	now: 67
+coverage: 81.818%	pattern: 17	before: 156	now: 156
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 214, fault_cnt:230
-coverage: 93.240%	pattern: 38	before: 67	now: 58
+[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 214, fault_cnt:222
+coverage: 83.800%	pattern: 18	before: 156	now: 139
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 93.240%	pattern: 38	before: 58	now: 58
+[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 86.946%	pattern: 19	before: 139	now: 112
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 93.240%	pattern: 38	before: 58	now: 58
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 87.179%	pattern: 20	before: 112	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 93.240%	pattern: 38	before: 58	now: 58
+coverage: 87.179%	pattern: 20	before: 110	now: 110
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 93.240%	pattern: 38	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
-coverage: 93.590%	pattern: 39	before: 58	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+[SOL] flip: 0, stem: 0, fault:92. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 87.762%	pattern: 21	before: 110	now: 105
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+coverage: 87.762%	pattern: 21	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 87.762%	pattern: 21	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 87.762%	pattern: 21	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 89.044%	pattern: 22	before: 105	now: 94
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 89.161%	pattern: 23	before: 94	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 89.394%	pattern: 24	before: 93	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 89.394%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 89.394%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 89.394%	pattern: 24	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 89.860%	pattern: 25	before: 91	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 89.977%	pattern: 26	before: 87	now: 86
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+coverage: 89.977%	pattern: 26	before: 86	now: 86
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 90.559%	pattern: 27	before: 86	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 90.676%	pattern: 28	before: 81	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 90.676%	pattern: 28	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 90.676%	pattern: 28	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 90.676%	pattern: 28	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 90.909%	pattern: 29	before: 80	now: 78
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 90.909%	pattern: 29	before: 78	now: 78
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 91.026%	pattern: 30	before: 78	now: 77
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+coverage: 91.026%	pattern: 30	before: 77	now: 77
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 91.259%	pattern: 31	before: 77	now: 75
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 91.608%	pattern: 32	before: 75	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 91.608%	pattern: 32	before: 72	now: 72
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+coverage: 91.608%	pattern: 32	before: 72	now: 72
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 92.075%	pattern: 33	before: 72	now: 68
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 93.590%	pattern: 39	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+coverage: 92.075%	pattern: 33	before: 68	now: 68
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+coverage: 92.075%	pattern: 33	before: 68	now: 68
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
-coverage: 93.590%	pattern: 39	before: 55	now: 55
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 92.075%	pattern: 33	before: 68	now: 68
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
-coverage: 94.755%	pattern: 40	before: 55	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
-coverage: 94.755%	pattern: 40	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
-coverage: 94.755%	pattern: 40	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 94.755%	pattern: 40	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 94.755%	pattern: 40	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 94.755%	pattern: 40	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
-coverage: 94.755%	pattern: 40	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 94.755%	pattern: 40	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
-coverage: 94.872%	pattern: 41	before: 45	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 94.872%	pattern: 41	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
-coverage: 95.338%	pattern: 42	before: 44	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 95.338%	pattern: 42	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 95.338%	pattern: 42	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 92.075%	pattern: 33	before: 68	now: 68
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+coverage: 92.075%	pattern: 33	before: 68	now: 68
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 92.075%	pattern: 33	before: 68	now: 68
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 92.075%	pattern: 33	before: 68	now: 68
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 92.191%	pattern: 34	before: 68	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 92.308%	pattern: 35	before: 67	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 92.308%	pattern: 35	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 92.308%	pattern: 35	before: 66	now: 66
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+coverage: 92.308%	pattern: 35	before: 66	now: 66
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 92.308%	pattern: 35	before: 66	now: 66
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 92.308%	pattern: 35	before: 66	now: 66
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 92.424%	pattern: 36	before: 66	now: 65
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+coverage: 92.424%	pattern: 36	before: 65	now: 65
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 92.424%	pattern: 36	before: 65	now: 65
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 92.424%	pattern: 36	before: 65	now: 65
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+coverage: 92.424%	pattern: 36	before: 65	now: 65
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 92.657%	pattern: 37	before: 65	now: 63
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
-coverage: 95.338%	pattern: 42	before: 40	now: 40
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 92.774%	pattern: 38	before: 63	now: 62
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:226
-coverage: 95.338%	pattern: 42	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 95.338%	pattern: 42	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 95.338%	pattern: 42	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
-coverage: 95.571%	pattern: 43	before: 40	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 95.571%	pattern: 43	before: 38	now: 38
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 92.774%	pattern: 38	before: 62	now: 62
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
-coverage: 95.571%	pattern: 43	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:218
-coverage: 95.688%	pattern: 44	before: 38	now: 37
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
-coverage: 95.688%	pattern: 44	before: 37	now: 37
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
-coverage: 95.688%	pattern: 44	before: 37	now: 37
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
-coverage: 95.688%	pattern: 44	before: 37	now: 37
+coverage: 92.774%	pattern: 38	before: 62	now: 62
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
-coverage: 95.688%	pattern: 44	before: 37	now: 37
+coverage: 92.774%	pattern: 38	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 92.774%	pattern: 38	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 92.890%	pattern: 39	before: 62	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 92.890%	pattern: 39	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 92.890%	pattern: 39	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 92.890%	pattern: 39	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 92.890%	pattern: 39	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 92.890%	pattern: 39	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 92.890%	pattern: 39	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 92.890%	pattern: 39	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 93.007%	pattern: 40	before: 61	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 93.007%	pattern: 40	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 93.007%	pattern: 40	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 93.007%	pattern: 40	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 93.007%	pattern: 40	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 93.007%	pattern: 40	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 93.007%	pattern: 40	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 93.007%	pattern: 40	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 93.007%	pattern: 40	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 93.124%	pattern: 41	before: 60	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 93.124%	pattern: 41	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 93.240%	pattern: 42	before: 59	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 93.240%	pattern: 42	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:66. flip_cnt: 0, stem_cnt: 214, fault_cnt:251
+coverage: 93.706%	pattern: 43	before: 58	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 93.706%	pattern: 43	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:146
+coverage: 93.706%	pattern: 43	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 93.706%	pattern: 43	before: 54	now: 54
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 95.688%	pattern: 44	before: 37	now: 37
+coverage: 93.706%	pattern: 43	before: 54	now: 54
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 95.688%	pattern: 44	before: 37	now: 37
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 93.706%	pattern: 43	before: 54	now: 54
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
-coverage: 95.688%	pattern: 44	before: 37	now: 37
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 93.706%	pattern: 43	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 93.823%	pattern: 44	before: 54	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 93.823%	pattern: 44	before: 53	now: 53
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
-coverage: 95.688%	pattern: 44	before: 37	now: 37
+coverage: 93.823%	pattern: 44	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 93.823%	pattern: 44	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 93.823%	pattern: 44	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 93.823%	pattern: 44	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 93.823%	pattern: 44	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 93.823%	pattern: 44	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 93.823%	pattern: 44	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 93.823%	pattern: 44	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 214, fault_cnt:223
+coverage: 94.639%	pattern: 45	before: 53	now: 46
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
-coverage: 95.688%	pattern: 44	before: 37	now: 37
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 94.639%	pattern: 45	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 94.988%	pattern: 46	before: 46	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 94.988%	pattern: 46	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 95.221%	pattern: 47	before: 43	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 95.221%	pattern: 47	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 95.221%	pattern: 47	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 95.221%	pattern: 47	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 95.221%	pattern: 47	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 95.221%	pattern: 47	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 95.338%	pattern: 48	before: 41	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 95.338%	pattern: 48	before: 40	now: 40
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
-coverage: 95.688%	pattern: 44	before: 37	now: 37
-checking valid circuit ... result: 1.   
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 95.338%	pattern: 48	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 95.688%	pattern: 49	before: 40	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:148
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 95.688%	pattern: 49	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 95.921%	pattern: 50	before: 37	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 95.921%	pattern: 50	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.037%	pattern: 51	before: 35	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:264
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:215
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:145
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.037%	pattern: 51	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.154%	pattern: 52	before: 34	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:148
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:309
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:257
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 96.154%	pattern: 52	before: 33	now: 33
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.503%	pattern: 53	before: 33	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:231
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.503%	pattern: 53	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:328
+coverage: 96.970%	pattern: 54	before: 30	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:145
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:213
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:217
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:225
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:220
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:224
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:223
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:314
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:254
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:309
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:261
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:210
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:216
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:218
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:209
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:207
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:209
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 96.970%	pattern: 54	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 97.086%	pattern: 55	before: 26	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:316
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:144
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:210
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:311
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:207
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:311
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.086%	pattern: 55	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.786%	pattern: 56	before: 25	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:213
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:311
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:143
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:215
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:213
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:148
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:207
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:214
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:148
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:221
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.786%	pattern: 56	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:328
+coverage: 97.902%	pattern: 57	before: 19	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:221
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:251
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:256
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:257
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:220
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:215
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:148
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:222
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:322
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:316
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:312
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:312
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:260
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:264
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:210
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:209
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:146
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:210
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:209
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:264
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:309
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:312
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:220
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:319
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:225
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:217
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:210
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 97.902%	pattern: 57	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:58. flip_cnt: 0, stem_cnt: 214, fault_cnt:260
+coverage: 98.368%	pattern: 58	before: 18	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:145
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:214
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:316
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:251
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:226
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:312
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:261
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:143
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:222
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:256
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:264
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:264
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:224
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:218
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:261
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.368%	pattern: 58	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:251
+coverage: 98.485%	pattern: 59	before: 14	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:222
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:317
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:209
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:313
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:223
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:209
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:313
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:148
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:251
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:223
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:257
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:210
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:261
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:209
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:262
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:314
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:142
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:203
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:311
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:256
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:209
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:254
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:218
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:247
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:219
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:260
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:309
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:146
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:312
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:311
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:260
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:229
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:310
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:146
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:321
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:148
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:215
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:219
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:262
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:262
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:259
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:150
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:215
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:260
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:257
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:206
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:201
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:313
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:207
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:311
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:141
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:313
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:207
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:215
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:255
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:144
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:267
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:250
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:321
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:143
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:250
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:269
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:296
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:149
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:264
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:248
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:262
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:303
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:301
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:197
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:229
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:264
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:313
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:212
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:271
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:307
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:305
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:273
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:319
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:275
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:306
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:264
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:263
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:285
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:220
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:304
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:278
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:308
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:225
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:283
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:299
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:302
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:277
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:281
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:272
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:286
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:258
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:300
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:274
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:279
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:290
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:291
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:289
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:266
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:292
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:270
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:265
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:282
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:276
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:295
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:223
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:280
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:297
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:284
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:288
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:287
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165
+coverage: 98.485%	pattern: 59	before: 13	now: 13
+checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_b12.bench.txt b/exp_result/ATPG-LS_b12.bench.txt
index 8b4a6f6..8f1c673 100644
--- a/exp_result/ATPG-LS_b12.bench.txt
+++ b/exp_result/ATPG-LS_b12.bench.txt
@@ -8,3 +8,2934 @@ Gate:	1039
 Stem:	511
 Level:	5
 ================================ 
+[SOL] flip: 0, stem: 0, fault:7336. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 31.906%	pattern: 1	before: 2078	now: 1415
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:5752. flip_cnt: 0, stem_cnt: 511, fault_cnt:685
+coverage: 52.839%	pattern: 2	before: 1415	now: 980
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:2787. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 60.154%	pattern: 3	before: 980	now: 828
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1039. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 63.956%	pattern: 4	before: 828	now: 749
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:796. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 66.073%	pattern: 5	before: 749	now: 705
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:566. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 67.565%	pattern: 6	before: 705	now: 674
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:544. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 69.153%	pattern: 7	before: 674	now: 641
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:580. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 71.511%	pattern: 8	before: 641	now: 592
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 72.281%	pattern: 9	before: 592	now: 576
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:324. flip_cnt: 0, stem_cnt: 511, fault_cnt:682
+coverage: 73.725%	pattern: 10	before: 576	now: 546
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 74.880%	pattern: 11	before: 546	now: 522
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 74.880%	pattern: 11	before: 522	now: 522
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 74.976%	pattern: 12	before: 522	now: 520
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:186. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 75.457%	pattern: 13	before: 520	now: 510
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:237. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 76.275%	pattern: 14	before: 510	now: 493
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 76.660%	pattern: 15	before: 493	now: 485
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 76.901%	pattern: 16	before: 485	now: 480
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 76.901%	pattern: 16	before: 480	now: 480
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 511, fault_cnt:610
+coverage: 77.575%	pattern: 17	before: 480	now: 466
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 77.671%	pattern: 18	before: 466	now: 464
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 78.200%	pattern: 19	before: 464	now: 453
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 78.393%	pattern: 20	before: 453	now: 449
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 78.970%	pattern: 21	before: 449	now: 437
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:262. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 79.644%	pattern: 22	before: 437	now: 423
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 79.836%	pattern: 23	before: 423	now: 419
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:113. flip_cnt: 0, stem_cnt: 511, fault_cnt:615
+coverage: 80.173%	pattern: 24	before: 419	now: 412
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 511, fault_cnt:606
+coverage: 80.414%	pattern: 25	before: 412	now: 407
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 80.799%	pattern: 26	before: 407	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 81.039%	pattern: 27	before: 399	now: 394
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 81.088%	pattern: 28	before: 394	now: 393
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 81.232%	pattern: 29	before: 393	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:614
+coverage: 81.232%	pattern: 29	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 81.232%	pattern: 29	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 81.424%	pattern: 30	before: 390	now: 386
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 81.521%	pattern: 31	before: 386	now: 384
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 81.521%	pattern: 31	before: 384	now: 384
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 81.809%	pattern: 32	before: 384	now: 378
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 81.809%	pattern: 32	before: 378	now: 378
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 511, fault_cnt:677
+coverage: 82.146%	pattern: 33	before: 378	now: 371
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:56. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 82.291%	pattern: 34	before: 371	now: 368
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 82.579%	pattern: 35	before: 368	now: 362
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 82.628%	pattern: 36	before: 362	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 82.820%	pattern: 37	before: 361	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:706
+coverage: 82.916%	pattern: 38	before: 357	now: 355
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 83.397%	pattern: 39	before: 355	now: 345
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 83.397%	pattern: 39	before: 345	now: 345
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 83.446%	pattern: 40	before: 345	now: 344
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 83.590%	pattern: 41	before: 344	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:612
+coverage: 83.638%	pattern: 42	before: 341	now: 340
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 511, fault_cnt:628
+coverage: 84.119%	pattern: 43	before: 340	now: 330
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:619
+coverage: 84.167%	pattern: 44	before: 330	now: 329
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 84.167%	pattern: 44	before: 329	now: 329
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 84.264%	pattern: 45	before: 329	now: 327
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:620
+coverage: 84.312%	pattern: 46	before: 327	now: 326
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 84.456%	pattern: 47	before: 326	now: 323
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 84.504%	pattern: 48	before: 323	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 84.697%	pattern: 49	before: 322	now: 318
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 84.697%	pattern: 49	before: 318	now: 318
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 84.697%	pattern: 49	before: 318	now: 318
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 84.697%	pattern: 49	before: 318	now: 318
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:41. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 84.937%	pattern: 50	before: 318	now: 313
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 84.937%	pattern: 50	before: 313	now: 313
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 84.986%	pattern: 51	before: 313	now: 312
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 85.178%	pattern: 52	before: 312	now: 308
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:671
+coverage: 85.226%	pattern: 53	before: 308	now: 307
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 511, fault_cnt:688
+coverage: 85.419%	pattern: 54	before: 307	now: 303
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 85.515%	pattern: 55	before: 303	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 511, fault_cnt:679
+coverage: 86.044%	pattern: 56	before: 301	now: 290
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:615
+coverage: 86.092%	pattern: 57	before: 290	now: 289
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 86.092%	pattern: 57	before: 289	now: 289
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 86.141%	pattern: 58	before: 289	now: 288
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 86.141%	pattern: 58	before: 288	now: 288
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 86.141%	pattern: 58	before: 288	now: 288
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 86.141%	pattern: 58	before: 288	now: 288
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 86.189%	pattern: 59	before: 288	now: 287
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 86.189%	pattern: 59	before: 287	now: 287
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 86.237%	pattern: 60	before: 287	now: 286
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 86.333%	pattern: 61	before: 286	now: 284
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 86.333%	pattern: 61	before: 284	now: 284
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:620
+coverage: 86.333%	pattern: 61	before: 284	now: 284
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 86.333%	pattern: 61	before: 284	now: 284
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 86.333%	pattern: 61	before: 284	now: 284
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 86.429%	pattern: 62	before: 284	now: 282
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 86.477%	pattern: 63	before: 282	now: 281
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 511, fault_cnt:618
+coverage: 86.526%	pattern: 64	before: 281	now: 280
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 86.526%	pattern: 64	before: 280	now: 280
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:183. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 87.007%	pattern: 65	before: 280	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 87.007%	pattern: 65	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 87.007%	pattern: 65	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 87.007%	pattern: 65	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 87.007%	pattern: 65	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 87.103%	pattern: 66	before: 270	now: 268
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:592
+coverage: 87.199%	pattern: 67	before: 268	now: 266
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:198. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 87.777%	pattern: 68	before: 266	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 87.777%	pattern: 68	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 87.969%	pattern: 69	before: 254	now: 250
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 88.065%	pattern: 70	before: 250	now: 248
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 88.065%	pattern: 70	before: 248	now: 248
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 511, fault_cnt:695
+coverage: 88.499%	pattern: 71	before: 248	now: 239
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:677
+coverage: 88.499%	pattern: 71	before: 239	now: 239
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 88.547%	pattern: 72	before: 239	now: 238
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 88.643%	pattern: 73	before: 238	now: 236
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 88.643%	pattern: 73	before: 236	now: 236
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 88.691%	pattern: 74	before: 236	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 88.835%	pattern: 75	before: 235	now: 232
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 88.835%	pattern: 75	before: 232	now: 232
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 88.835%	pattern: 75	before: 232	now: 232
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 88.835%	pattern: 75	before: 232	now: 232
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 88.835%	pattern: 75	before: 232	now: 232
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:606
+coverage: 88.835%	pattern: 75	before: 232	now: 232
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 88.835%	pattern: 75	before: 232	now: 232
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:81. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 89.124%	pattern: 76	before: 232	now: 226
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 89.124%	pattern: 76	before: 226	now: 226
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 89.172%	pattern: 77	before: 226	now: 225
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 89.172%	pattern: 77	before: 225	now: 225
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 89.172%	pattern: 77	before: 225	now: 225
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 89.220%	pattern: 78	before: 225	now: 224
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 89.220%	pattern: 78	before: 224	now: 224
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 89.220%	pattern: 78	before: 224	now: 224
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 89.220%	pattern: 78	before: 224	now: 224
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 89.317%	pattern: 79	before: 224	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:676
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:679
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:631
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:690
+coverage: 89.317%	pattern: 79	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 89.413%	pattern: 80	before: 222	now: 220
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 89.413%	pattern: 80	before: 220	now: 220
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 89.413%	pattern: 80	before: 220	now: 220
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 89.413%	pattern: 80	before: 220	now: 220
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 89.461%	pattern: 81	before: 220	now: 219
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 89.461%	pattern: 81	before: 219	now: 219
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:58. flip_cnt: 0, stem_cnt: 511, fault_cnt:695
+coverage: 89.654%	pattern: 82	before: 219	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:618
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:604
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 89.654%	pattern: 82	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 89.702%	pattern: 83	before: 215	now: 214
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 89.702%	pattern: 83	before: 214	now: 214
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:602
+coverage: 89.702%	pattern: 83	before: 214	now: 214
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 89.702%	pattern: 83	before: 214	now: 214
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:687
+coverage: 89.702%	pattern: 83	before: 214	now: 214
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 89.750%	pattern: 84	before: 214	now: 213
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 89.750%	pattern: 84	before: 213	now: 213
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 89.750%	pattern: 84	before: 213	now: 213
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 89.750%	pattern: 84	before: 213	now: 213
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 89.750%	pattern: 84	before: 213	now: 213
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 89.750%	pattern: 84	before: 213	now: 213
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:619
+coverage: 89.798%	pattern: 85	before: 213	now: 212
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 89.798%	pattern: 85	before: 212	now: 212
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 89.798%	pattern: 85	before: 212	now: 212
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 89.846%	pattern: 86	before: 212	now: 211
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 89.846%	pattern: 86	before: 211	now: 211
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 89.894%	pattern: 87	before: 211	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:602
+coverage: 89.942%	pattern: 88	before: 210	now: 209
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 89.942%	pattern: 88	before: 209	now: 209
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 89.942%	pattern: 88	before: 209	now: 209
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 89.942%	pattern: 88	before: 209	now: 209
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:622
+coverage: 89.990%	pattern: 89	before: 209	now: 208
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 89.990%	pattern: 89	before: 208	now: 208
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 511, fault_cnt:620
+coverage: 90.231%	pattern: 90	before: 208	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 90.231%	pattern: 90	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 90.231%	pattern: 90	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 90.279%	pattern: 91	before: 203	now: 202
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 90.279%	pattern: 91	before: 202	now: 202
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 90.279%	pattern: 91	before: 202	now: 202
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:594
+coverage: 90.279%	pattern: 91	before: 202	now: 202
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 90.279%	pattern: 91	before: 202	now: 202
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 90.279%	pattern: 91	before: 202	now: 202
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 90.327%	pattern: 92	before: 202	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:671
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 90.327%	pattern: 92	before: 201	now: 201
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 90.375%	pattern: 93	before: 201	now: 200
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 90.375%	pattern: 93	before: 200	now: 200
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 90.375%	pattern: 93	before: 200	now: 200
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:678
+coverage: 90.375%	pattern: 93	before: 200	now: 200
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 90.375%	pattern: 93	before: 200	now: 200
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:617
+coverage: 90.375%	pattern: 93	before: 200	now: 200
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 90.375%	pattern: 93	before: 200	now: 200
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 90.375%	pattern: 93	before: 200	now: 200
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 90.423%	pattern: 94	before: 200	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:613
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:596
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:604
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 90.423%	pattern: 94	before: 199	now: 199
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 90.616%	pattern: 95	before: 199	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:683
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:693
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:691
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:628
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:608
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:601
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:692
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 90.616%	pattern: 95	before: 195	now: 195
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 90.712%	pattern: 96	before: 195	now: 193
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 90.712%	pattern: 96	before: 193	now: 193
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:77. flip_cnt: 0, stem_cnt: 511, fault_cnt:691
+coverage: 90.953%	pattern: 97	before: 193	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:596
+coverage: 90.953%	pattern: 97	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 90.953%	pattern: 97	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 90.953%	pattern: 97	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 90.953%	pattern: 97	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 90.953%	pattern: 97	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 90.953%	pattern: 97	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 90.953%	pattern: 97	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 90.953%	pattern: 97	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:687
+coverage: 91.001%	pattern: 98	before: 188	now: 187
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 91.001%	pattern: 98	before: 187	now: 187
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 91.001%	pattern: 98	before: 187	now: 187
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:597
+coverage: 91.049%	pattern: 99	before: 187	now: 186
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 91.290%	pattern: 100	before: 186	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:590
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:700
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:703
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:685
+coverage: 91.290%	pattern: 100	before: 181	now: 181
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:93. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 91.578%	pattern: 101	before: 181	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 91.578%	pattern: 101	before: 175	now: 175
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 91.627%	pattern: 102	before: 175	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 91.627%	pattern: 102	before: 174	now: 174
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:688
+coverage: 91.723%	pattern: 103	before: 174	now: 172
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 91.771%	pattern: 104	before: 172	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:594
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:619
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:690
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:678
+coverage: 91.771%	pattern: 104	before: 171	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 91.819%	pattern: 105	before: 171	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 91.963%	pattern: 106	before: 170	now: 167
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:705
+coverage: 92.012%	pattern: 107	before: 167	now: 166
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 92.060%	pattern: 108	before: 166	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:603
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:685
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:606
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:604
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:692
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.060%	pattern: 108	before: 165	now: 165
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 92.108%	pattern: 109	before: 165	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:676
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:690
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:678
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:684
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:696
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.108%	pattern: 109	before: 164	now: 164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.204%	pattern: 110	before: 164	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:613
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:601
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:602
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:617
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:682
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.204%	pattern: 110	before: 162	now: 162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 92.300%	pattern: 111	before: 162	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:676
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:678
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:671
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:694
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:611
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:678
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:608
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:617
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:628
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:677
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:620
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:687
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:603
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:676
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 92.300%	pattern: 111	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 511, fault_cnt:631
+coverage: 92.397%	pattern: 112	before: 160	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:686
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:631
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:626
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:676
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 92.397%	pattern: 112	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 92.445%	pattern: 113	before: 158	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:679
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:595
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:676
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:594
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:576
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:628
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:700
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:697
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:626
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:700
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:684
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:598
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:599
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:628
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:685
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:631
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:626
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:678
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:618
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:613
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:614
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.445%	pattern: 113	before: 157	now: 157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 92.493%	pattern: 114	before: 157	now: 156
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 92.541%	pattern: 115	before: 156	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:677
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:618
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:691
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:603
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:601
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:617
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:608
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:620
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:695
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:698
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 92.541%	pattern: 115	before: 155	now: 155
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 92.589%	pattern: 116	before: 155	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:704
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:671
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:618
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:597
+coverage: 92.589%	pattern: 116	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 92.637%	pattern: 117	before: 154	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:676
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:619
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:678
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:691
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:677
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:684
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:620
+coverage: 92.637%	pattern: 117	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:714
+coverage: 92.685%	pattern: 118	before: 153	now: 152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 92.685%	pattern: 118	before: 152	now: 152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.685%	pattern: 118	before: 152	now: 152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 92.685%	pattern: 118	before: 152	now: 152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:588
+coverage: 92.685%	pattern: 118	before: 152	now: 152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 92.685%	pattern: 118	before: 152	now: 152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 92.685%	pattern: 118	before: 152	now: 152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 92.733%	pattern: 119	before: 152	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:621
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:621
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:628
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:602
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:619
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:626
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:670
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:614
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:697
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:618
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:589
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:611
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:602
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:682
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:686
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:589
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 92.733%	pattern: 119	before: 151	now: 151
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:501. flip_cnt: 0, stem_cnt: 511, fault_cnt:690
+coverage: 94.273%	pattern: 120	before: 151	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:599
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:631
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:601
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:611
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:690
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:700
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:683
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:689
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 94.273%	pattern: 120	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 94.321%	pattern: 121	before: 119	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:684
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:596
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:603
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:620
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:700
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:614
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:626
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:674
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:611
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:692
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:597
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:628
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:688
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:702
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:677
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:609
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:679
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:678
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:613
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:698
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:619
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:618
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:653
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:655
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:585
+coverage: 94.321%	pattern: 121	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 511, fault_cnt:685
+coverage: 94.370%	pattern: 122	before: 118	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:671
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:616
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:638
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:640
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:680
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:626
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:657
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:606
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:663
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:677
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:673
+coverage: 94.370%	pattern: 122	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:14. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 94.418%	pattern: 123	before: 117	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:634
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:619
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:694
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:612
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:669
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:607
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:633
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:668
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:683
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:629
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:672
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:650
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:602
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:622
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:628
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:662
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:648
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:658
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:636
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:661
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:659
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:691
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:656
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:690
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:677
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:651
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:625
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:618
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:654
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:683
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:643
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:652
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:642
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:667
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:613
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:649
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:665
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:660
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:685
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:692
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:666
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:631
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:623
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:630
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:675
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:664
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:683
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:671
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:682
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:645
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:647
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:627
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:635
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:644
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:632
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:637
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:676
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:646
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:641
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:681
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:624
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 511, fault_cnt:639
+coverage: 94.418%	pattern: 123	before: 116	now: 116
+checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_b13.bench.txt b/exp_result/ATPG-LS_b13.bench.txt
index 6c352fb..17f4682 100644
--- a/exp_result/ATPG-LS_b13.bench.txt
+++ b/exp_result/ATPG-LS_b13.bench.txt
@@ -8,357 +8,108621 @@ Gate:	322
 Stem:	187
 Level:	3
 ================================ 
-[SOL] flip: 0, stem: 0, fault:4104. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
-coverage: 33.540%	pattern: 1	before: 644	now: 428
+[SOL] flip: 0, stem: 0, fault:2149. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 34.783%	pattern: 1	before: 644	now: 420
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2470. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 53.727%	pattern: 2	before: 428	now: 298
+[SOL] flip: 0, stem: 0, fault:900. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 59.627%	pattern: 2	before: 420	now: 260
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1140. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
-coverage: 63.043%	pattern: 3	before: 298	now: 238
+[SOL] flip: 0, stem: 0, fault:627. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 70.807%	pattern: 3	before: 260	now: 188
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:570. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
-coverage: 67.702%	pattern: 4	before: 238	now: 208
+[SOL] flip: 0, stem: 0, fault:433. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 75.311%	pattern: 4	before: 188	now: 159
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
-coverage: 70.031%	pattern: 5	before: 208	now: 193
+[SOL] flip: 0, stem: 0, fault:369. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 81.832%	pattern: 5	before: 159	now: 117
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
-coverage: 71.739%	pattern: 6	before: 193	now: 182
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 83.851%	pattern: 6	before: 117	now: 104
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
-coverage: 72.360%	pattern: 7	before: 182	now: 178
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 85.559%	pattern: 7	before: 104	now: 93
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
-coverage: 74.068%	pattern: 8	before: 178	now: 167
+[SOL] flip: 0, stem: 0, fault:122. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 86.801%	pattern: 8	before: 93	now: 85
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 75.932%	pattern: 9	before: 167	now: 155
+[SOL] flip: 0, stem: 0, fault:90. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 89.286%	pattern: 9	before: 85	now: 69
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 78.261%	pattern: 10	before: 155	now: 140
+[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 89.907%	pattern: 10	before: 69	now: 65
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 78.571%	pattern: 11	before: 140	now: 138
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
-coverage: 78.571%	pattern: 11	before: 138	now: 138
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 79.814%	pattern: 12	before: 138	now: 130
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 80.590%	pattern: 13	before: 130	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
-coverage: 81.832%	pattern: 14	before: 125	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 81.832%	pattern: 14	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
-coverage: 81.832%	pattern: 14	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
-coverage: 83.385%	pattern: 15	before: 117	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 83.385%	pattern: 15	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
-coverage: 84.317%	pattern: 16	before: 107	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
-coverage: 85.093%	pattern: 17	before: 101	now: 96
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 85.248%	pattern: 18	before: 96	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
-coverage: 85.248%	pattern: 18	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
-coverage: 85.248%	pattern: 18	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
-coverage: 85.714%	pattern: 19	before: 95	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
-coverage: 85.714%	pattern: 19	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
-coverage: 85.714%	pattern: 19	before: 92	now: 92
+[SOL] flip: 0, stem: 0, fault:37. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 92.236%	pattern: 11	before: 65	now: 50
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
-coverage: 85.714%	pattern: 19	before: 92	now: 92
+coverage: 92.236%	pattern: 11	before: 50	now: 50
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
-coverage: 85.714%	pattern: 19	before: 92	now: 92
+[SOL] flip: 0, stem: 0, fault:141. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 93.634%	pattern: 12	before: 50	now: 41
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
-coverage: 86.646%	pattern: 20	before: 92	now: 86
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 93.789%	pattern: 13	before: 41	now: 40
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 86.646%	pattern: 20	before: 86	now: 86
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 94.255%	pattern: 14	before: 40	now: 37
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
-coverage: 86.646%	pattern: 20	before: 86	now: 86
+[SOL] flip: 0, stem: 0, fault:21. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 94.720%	pattern: 15	before: 37	now: 34
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 86.646%	pattern: 20	before: 86	now: 86
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 94.876%	pattern: 16	before: 34	now: 33
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
-coverage: 86.646%	pattern: 20	before: 86	now: 86
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 95.186%	pattern: 17	before: 33	now: 31
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
-coverage: 86.646%	pattern: 20	before: 86	now: 86
+[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 95.342%	pattern: 18	before: 31	now: 30
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
-coverage: 86.646%	pattern: 20	before: 86	now: 86
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 95.497%	pattern: 19	before: 30	now: 29
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
-coverage: 90.839%	pattern: 21	before: 86	now: 59
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 95.652%	pattern: 20	before: 29	now: 28
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 90.839%	pattern: 21	before: 59	now: 59
+[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 95.963%	pattern: 21	before: 28	now: 26
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
-coverage: 90.839%	pattern: 21	before: 59	now: 59
+[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 96.118%	pattern: 22	before: 26	now: 25
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 90.839%	pattern: 21	before: 59	now: 59
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 96.118%	pattern: 22	before: 25	now: 25
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
-coverage: 91.770%	pattern: 22	before: 59	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
-coverage: 91.925%	pattern: 23	before: 53	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
-coverage: 91.925%	pattern: 23	before: 52	now: 52
+[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 96.273%	pattern: 23	before: 25	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
-coverage: 91.925%	pattern: 23	before: 52	now: 52
+coverage: 96.273%	pattern: 23	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 96.273%	pattern: 23	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 96.739%	pattern: 24	before: 24	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 96.739%	pattern: 24	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 96.739%	pattern: 24	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 96.894%	pattern: 25	before: 21	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 96.894%	pattern: 25	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 96.894%	pattern: 25	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 96.894%	pattern: 25	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.050%	pattern: 26	before: 20	now: 19
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 91.925%	pattern: 23	before: 52	now: 52
+coverage: 97.050%	pattern: 26	before: 19	now: 19
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
-coverage: 91.925%	pattern: 23	before: 52	now: 52
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.050%	pattern: 26	before: 19	now: 19
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 91.925%	pattern: 23	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:25. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 92.702%	pattern: 24	before: 52	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
-coverage: 92.702%	pattern: 24	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
-coverage: 92.702%	pattern: 24	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 92.702%	pattern: 24	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
-coverage: 92.702%	pattern: 24	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
-coverage: 92.857%	pattern: 25	before: 47	now: 46
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
-coverage: 92.857%	pattern: 25	before: 46	now: 46
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
-coverage: 92.857%	pattern: 25	before: 46	now: 46
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 93.012%	pattern: 26	before: 46	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 93.012%	pattern: 26	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
-coverage: 93.012%	pattern: 26	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
-coverage: 93.012%	pattern: 26	before: 45	now: 45
+coverage: 97.050%	pattern: 26	before: 19	now: 19
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
-coverage: 93.012%	pattern: 26	before: 45	now: 45
+coverage: 97.050%	pattern: 26	before: 19	now: 19
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
-coverage: 93.012%	pattern: 26	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
-coverage: 93.012%	pattern: 26	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
-coverage: 93.012%	pattern: 26	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
-coverage: 93.012%	pattern: 26	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
-coverage: 93.168%	pattern: 27	before: 45	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
-coverage: 93.323%	pattern: 28	before: 44	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
-coverage: 93.789%	pattern: 29	before: 43	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
-coverage: 93.789%	pattern: 29	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:36. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
-coverage: 94.099%	pattern: 30	before: 40	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
-coverage: 94.255%	pattern: 31	before: 38	now: 37
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 97.050%	pattern: 26	before: 19	now: 19
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
-coverage: 94.255%	pattern: 31	before: 37	now: 37
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 94.410%	pattern: 32	before: 37	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
-coverage: 94.410%	pattern: 32	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 94.410%	pattern: 32	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
-coverage: 94.410%	pattern: 32	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
-coverage: 94.410%	pattern: 32	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 94.410%	pattern: 32	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
-coverage: 94.410%	pattern: 32	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 94.410%	pattern: 32	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
-coverage: 94.410%	pattern: 32	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
-coverage: 95.186%	pattern: 33	before: 36	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
-coverage: 95.186%	pattern: 33	before: 31	now: 31
+coverage: 97.050%	pattern: 26	before: 19	now: 19
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
-coverage: 95.186%	pattern: 33	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
-coverage: 95.342%	pattern: 34	before: 31	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
-coverage: 95.342%	pattern: 34	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 95.342%	pattern: 34	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
-coverage: 95.342%	pattern: 34	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
-coverage: 95.342%	pattern: 34	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
-coverage: 95.342%	pattern: 34	before: 30	now: 30
+coverage: 97.050%	pattern: 26	before: 19	now: 19
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
-coverage: 95.342%	pattern: 34	before: 30	now: 30
+coverage: 97.050%	pattern: 26	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.050%	pattern: 26	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.050%	pattern: 26	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.050%	pattern: 26	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.050%	pattern: 26	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.050%	pattern: 26	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 19	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
-coverage: 95.342%	pattern: 34	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 95.342%	pattern: 34	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
-coverage: 95.342%	pattern: 34	before: 30	now: 30
+coverage: 97.205%	pattern: 27	before: 18	now: 18
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
-coverage: 95.342%	pattern: 34	before: 30	now: 30
+coverage: 97.205%	pattern: 27	before: 18	now: 18
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
-coverage: 95.342%	pattern: 34	before: 30	now: 30
+coverage: 97.205%	pattern: 27	before: 18	now: 18
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
-coverage: 95.652%	pattern: 35	before: 30	now: 28
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.205%	pattern: 27	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:21. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 97.671%	pattern: 28	before: 18	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 97.671%	pattern: 28	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:85. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 15	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:199
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:196
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:255
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:197
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:260
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.447%	pattern: 29	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 10	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:199
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:198
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:199
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:199
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:254
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:199
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:199
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:254
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:256
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:199
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:253
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:254
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:198
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:197
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:254
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:254
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:254
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:255
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:255
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:253
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:198
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:254
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:243
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:258
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:250
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:251
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:201
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:244
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:254
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:253
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:255
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:239
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:248
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:249
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:236
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:245
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:247
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:200
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:242
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:240
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:252
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:246
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:203
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:237
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:206
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:207
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:234
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:211
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:238
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:232
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:241
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:233
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:199
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:210
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:209
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:202
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:205
+coverage: 98.602%	pattern: 30	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216
+coverage: 98.602%	pattern: 30	before: 9	now: 9
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_b20.bench.txt b/exp_result/ATPG-LS_b20.bench.txt
index 786e44c..08ec913 100644
--- a/exp_result/ATPG-LS_b20.bench.txt
+++ b/exp_result/ATPG-LS_b20.bench.txt
@@ -8,3 +8,72 @@ Gate:	8734
 Stem:	3428
 Level:	7
 ================================ 
+[SOL] flip: 0, stem: 0, fault:49107. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3179
+coverage: 18.199%	pattern: 1	before: 17468	now: 14289
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:28816. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3009
+coverage: 27.908%	pattern: 2	before: 14289	now: 12593
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:31154. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3635
+coverage: 37.423%	pattern: 3	before: 12593	now: 10931
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:7652. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2945
+coverage: 39.873%	pattern: 4	before: 10931	now: 10503
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3885. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3014
+coverage: 41.127%	pattern: 5	before: 10503	now: 10284
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:5760. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3259
+coverage: 42.896%	pattern: 6	before: 10284	now: 9975
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1034. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3045
+coverage: 43.222%	pattern: 7	before: 9975	now: 9918
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1011. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2979
+coverage: 43.537%	pattern: 8	before: 9918	now: 9863
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:381. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2987
+coverage: 43.657%	pattern: 9	before: 9863	now: 9842
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:10489. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3399
+coverage: 46.823%	pattern: 10	before: 9842	now: 9289
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:153. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2905
+coverage: 46.874%	pattern: 11	before: 9289	now: 9280
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:5681. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3417
+coverage: 48.586%	pattern: 12	before: 9280	now: 8981
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:63. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3038
+coverage: 48.615%	pattern: 13	before: 8981	now: 8976
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2944
+coverage: 48.632%	pattern: 14	before: 8976	now: 8973
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3002
+coverage: 48.655%	pattern: 15	before: 8973	now: 8969
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2898
+coverage: 48.666%	pattern: 16	before: 8969	now: 8967
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3189
+coverage: 48.683%	pattern: 17	before: 8967	now: 8964
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3016
+coverage: 48.683%	pattern: 17	before: 8964	now: 8964
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:2987
+coverage: 48.683%	pattern: 17	before: 8964	now: 8964
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3030
+coverage: 48.695%	pattern: 18	before: 8964	now: 8962
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3133
+coverage: 48.695%	pattern: 18	before: 8962	now: 8962
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:874. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3187
+coverage: 48.958%	pattern: 19	before: 8962	now: 8916
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3428, fault_cnt:3076
+coverage: 48.958%	pattern: 19	before: 8916	now: 8916
+checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_b21.bench.txt b/exp_result/ATPG-LS_b21.bench.txt
index 9906514..085bc20 100644
--- a/exp_result/ATPG-LS_b21.bench.txt
+++ b/exp_result/ATPG-LS_b21.bench.txt
@@ -8,3 +8,69 @@ Gate:	8995
 Stem:	3647
 Level:	8
 ================================ 
+[SOL] flip: 0, stem: 0, fault:51387. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2917
+coverage: 16.215%	pattern: 1	before: 17990	now: 15073
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:31083. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2990
+coverage: 26.148%	pattern: 2	before: 15073	now: 13286
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:13816. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2964
+coverage: 30.812%	pattern: 3	before: 13286	now: 12447
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:8210. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2890
+coverage: 33.346%	pattern: 4	before: 12447	now: 11991
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:14317. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3232
+coverage: 37.599%	pattern: 5	before: 11991	now: 11226
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:2900. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2982
+coverage: 38.471%	pattern: 6	before: 11226	now: 11069
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1253. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3028
+coverage: 38.844%	pattern: 7	before: 11069	now: 11002
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3176. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2858
+coverage: 39.789%	pattern: 8	before: 11002	now: 10832
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:5492. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3168
+coverage: 41.401%	pattern: 9	before: 10832	now: 10542
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:290. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2893
+coverage: 41.501%	pattern: 10	before: 10542	now: 10524
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:382. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2988
+coverage: 41.618%	pattern: 11	before: 10524	now: 10503
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:191. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2956
+coverage: 41.679%	pattern: 12	before: 10503	now: 10492
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2804
+coverage: 41.723%	pattern: 13	before: 10492	now: 10484
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1750. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2770
+coverage: 42.240%	pattern: 14	before: 10484	now: 10391
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:78. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2984
+coverage: 42.268%	pattern: 15	before: 10391	now: 10386
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2959
+coverage: 42.279%	pattern: 16	before: 10386	now: 10384
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2897
+coverage: 42.279%	pattern: 16	before: 10384	now: 10384
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3610. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3191
+coverage: 43.335%	pattern: 17	before: 10384	now: 10194
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3083
+coverage: 43.485%	pattern: 18	before: 10194	now: 10167
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2897
+coverage: 43.513%	pattern: 19	before: 10167	now: 10162
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1501. flip_cnt: 0, stem_cnt: 3647, fault_cnt:2843
+coverage: 43.952%	pattern: 20	before: 10162	now: 10083
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:4629. flip_cnt: 0, stem_cnt: 3647, fault_cnt:3206
+coverage: 45.309%	pattern: 21	before: 10083	now: 9839
+checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_b22.bench.txt b/exp_result/ATPG-LS_b22.bench.txt
index c5c89e5..73df137 100644
--- a/exp_result/ATPG-LS_b22.bench.txt
+++ b/exp_result/ATPG-LS_b22.bench.txt
@@ -8,3 +8,15 @@ Gate:	13721
 Stem:	5379
 Level:	8
 ================================ 
+[SOL] flip: 0, stem: 0, fault:75481. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4379
+coverage: 15.957%	pattern: 1	before: 27442	now: 23063
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:42481. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4587
+coverage: 24.299%	pattern: 2	before: 23063	now: 20774
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19160. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4476
+coverage: 28.613%	pattern: 3	before: 20774	now: 19590
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:10322. flip_cnt: 0, stem_cnt: 5379, fault_cnt:4248
+coverage: 30.701%	pattern: 4	before: 19590	now: 19017
+checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_c1355.bench.txt b/exp_result/ATPG-LS_c1355.bench.txt
index 7bd0690..37deda7 100644
--- a/exp_result/ATPG-LS_c1355.bench.txt
+++ b/exp_result/ATPG-LS_c1355.bench.txt
@@ -8,44013 +8,12226 @@ Gate:	587
 Stem:	299
 Level:	7
 ================================ 
-[SOL] flip: 0, stem: 0, fault:5058. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 30.068%	pattern: 1	before: 1174	now: 821
+[SOL] flip: 0, stem: 0, fault:2347. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 16.354%	pattern: 1	before: 1174	now: 982
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4128. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
-coverage: 51.363%	pattern: 2	before: 821	now: 571
+[SOL] flip: 0, stem: 0, fault:902. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 24.702%	pattern: 2	before: 982	now: 884
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:333. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 54.344%	pattern: 3	before: 571	now: 536
+[SOL] flip: 0, stem: 0, fault:614. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 30.239%	pattern: 3	before: 884	now: 819
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:280. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 55.622%	pattern: 4	before: 536	now: 521
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 60.307%	pattern: 5	before: 521	now: 466
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:551. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 62.777%	pattern: 6	before: 466	now: 437
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:551. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 65.247%	pattern: 7	before: 437	now: 408
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 67.632%	pattern: 8	before: 408	now: 380
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 72.317%	pattern: 9	before: 380	now: 325
+[SOL] flip: 0, stem: 0, fault:1689. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 38.330%	pattern: 4	before: 819	now: 724
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 72.317%	pattern: 9	before: 325	now: 325
+coverage: 38.330%	pattern: 4	before: 724	now: 724
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:2508. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 49.574%	pattern: 5	before: 724	now: 592
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1174. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 54.855%	pattern: 6	before: 592	now: 530
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 72.317%	pattern: 9	before: 325	now: 325
+coverage: 54.855%	pattern: 6	before: 530	now: 530
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1368. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 60.988%	pattern: 7	before: 530	now: 458
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 60.988%	pattern: 7	before: 458	now: 458
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:703. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 64.140%	pattern: 8	before: 458	now: 421
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1938. flip_cnt: 0, stem_cnt: 299, fault_cnt:462
+coverage: 72.828%	pattern: 9	before: 421	now: 319
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 299, fault_cnt:292
+coverage: 75.128%	pattern: 10	before: 319	now: 292
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 75.639%	pattern: 11	before: 292	now: 286
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 77.853%	pattern: 12	before: 286	now: 260
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 77.853%	pattern: 12	before: 260	now: 260
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 77.853%	pattern: 12	before: 260	now: 260
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 72.317%	pattern: 9	before: 325	now: 325
+coverage: 77.853%	pattern: 12	before: 260	now: 260
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 72.317%	pattern: 9	before: 325	now: 325
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 72.317%	pattern: 9	before: 325	now: 325
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 72.402%	pattern: 10	before: 325	now: 324
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 74.446%	pattern: 11	before: 324	now: 300
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 75.724%	pattern: 12	before: 300	now: 285
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 77.939%	pattern: 13	before: 285	now: 259
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 78.279%	pattern: 14	before: 259	now: 255
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 78.279%	pattern: 14	before: 255	now: 255
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 79.557%	pattern: 15	before: 255	now: 240
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 79.557%	pattern: 15	before: 240	now: 240
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 81.261%	pattern: 16	before: 240	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 81.261%	pattern: 16	before: 220	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 81.261%	pattern: 16	before: 220	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 81.261%	pattern: 16	before: 220	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 81.261%	pattern: 16	before: 220	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 81.261%	pattern: 16	before: 220	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 81.261%	pattern: 16	before: 220	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 81.261%	pattern: 16	before: 220	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 81.261%	pattern: 16	before: 220	now: 220
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 81.857%	pattern: 17	before: 220	now: 213
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 81.942%	pattern: 18	before: 213	now: 212
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 82.709%	pattern: 19	before: 212	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 83.135%	pattern: 20	before: 203	now: 198
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 83.560%	pattern: 21	before: 198	now: 193
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 83.560%	pattern: 21	before: 193	now: 193
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 83.731%	pattern: 22	before: 193	now: 191
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 83.816%	pattern: 23	before: 191	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 83.816%	pattern: 23	before: 190	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 83.816%	pattern: 23	before: 190	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 83.816%	pattern: 23	before: 190	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 83.816%	pattern: 23	before: 190	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 84.668%	pattern: 24	before: 190	now: 180
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 84.838%	pattern: 25	before: 180	now: 178
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 84.838%	pattern: 25	before: 178	now: 178
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 84.838%	pattern: 25	before: 178	now: 178
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 84.838%	pattern: 25	before: 178	now: 178
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 85.264%	pattern: 26	before: 178	now: 173
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 85.264%	pattern: 26	before: 173	now: 173
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 85.264%	pattern: 26	before: 173	now: 173
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 85.264%	pattern: 26	before: 173	now: 173
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 85.264%	pattern: 26	before: 173	now: 173
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 85.264%	pattern: 26	before: 173	now: 173
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 85.264%	pattern: 26	before: 173	now: 173
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 85.349%	pattern: 27	before: 173	now: 172
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 86.201%	pattern: 28	before: 172	now: 162
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 86.201%	pattern: 28	before: 162	now: 162
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 86.201%	pattern: 28	before: 162	now: 162
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 86.712%	pattern: 29	before: 162	now: 156
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 86.797%	pattern: 30	before: 156	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 86.797%	pattern: 30	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 86.797%	pattern: 30	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 86.797%	pattern: 30	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 86.797%	pattern: 30	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 86.882%	pattern: 31	before: 155	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 86.882%	pattern: 31	before: 154	now: 154
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 87.053%	pattern: 32	before: 154	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 87.053%	pattern: 32	before: 152	now: 152
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 87.223%	pattern: 33	before: 152	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 87.223%	pattern: 33	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 87.223%	pattern: 33	before: 150	now: 150
+[SOL] flip: 0, stem: 0, fault:1064. flip_cnt: 0, stem_cnt: 299, fault_cnt:467
+coverage: 82.624%	pattern: 13	before: 260	now: 204
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 87.394%	pattern: 34	before: 150	now: 148
+coverage: 82.794%	pattern: 14	before: 204	now: 202
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 87.394%	pattern: 34	before: 148	now: 148
+coverage: 82.794%	pattern: 14	before: 202	now: 202
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 83.816%	pattern: 15	before: 202	now: 190
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 87.394%	pattern: 34	before: 148	now: 148
+coverage: 83.816%	pattern: 15	before: 190	now: 190
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 87.394%	pattern: 34	before: 148	now: 148
+[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 84.923%	pattern: 16	before: 190	now: 177
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 87.394%	pattern: 34	before: 148	now: 148
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 85.349%	pattern: 17	before: 177	now: 172
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 88.160%	pattern: 35	before: 148	now: 139
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 88.160%	pattern: 35	before: 139	now: 139
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 88.160%	pattern: 35	before: 139	now: 139
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 88.160%	pattern: 35	before: 139	now: 139
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 88.160%	pattern: 35	before: 139	now: 139
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 88.245%	pattern: 36	before: 139	now: 138
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 88.245%	pattern: 36	before: 138	now: 138
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 88.330%	pattern: 37	before: 138	now: 137
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 88.330%	pattern: 37	before: 137	now: 137
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 88.330%	pattern: 37	before: 137	now: 137
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 88.330%	pattern: 37	before: 137	now: 137
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 88.330%	pattern: 37	before: 137	now: 137
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 89.267%	pattern: 38	before: 137	now: 126
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 86.371%	pattern: 18	before: 172	now: 160
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 89.267%	pattern: 38	before: 126	now: 126
+coverage: 86.371%	pattern: 18	before: 160	now: 160
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 89.267%	pattern: 38	before: 126	now: 126
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 89.267%	pattern: 38	before: 126	now: 126
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 89.353%	pattern: 39	before: 126	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 89.353%	pattern: 39	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 89.353%	pattern: 39	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 89.353%	pattern: 39	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 89.523%	pattern: 40	before: 125	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 89.523%	pattern: 40	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 89.523%	pattern: 40	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 89.523%	pattern: 40	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 89.523%	pattern: 40	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 89.523%	pattern: 40	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 89.523%	pattern: 40	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 89.523%	pattern: 40	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 89.523%	pattern: 40	before: 123	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 90.375%	pattern: 41	before: 123	now: 113
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 90.375%	pattern: 41	before: 113	now: 113
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.375%	pattern: 41	before: 113	now: 113
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 90.375%	pattern: 41	before: 113	now: 113
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 90.460%	pattern: 42	before: 113	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 90.460%	pattern: 42	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 90.630%	pattern: 43	before: 112	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.630%	pattern: 43	before: 110	now: 110
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 90.716%	pattern: 44	before: 110	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.716%	pattern: 44	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.716%	pattern: 44	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.716%	pattern: 44	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 90.886%	pattern: 45	before: 109	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 90.971%	pattern: 46	before: 107	now: 106
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 90.971%	pattern: 46	before: 106	now: 106
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 90.971%	pattern: 46	before: 106	now: 106
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.971%	pattern: 46	before: 106	now: 106
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.971%	pattern: 46	before: 106	now: 106
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 90.971%	pattern: 46	before: 106	now: 106
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 90.971%	pattern: 46	before: 106	now: 106
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 90.971%	pattern: 46	before: 106	now: 106
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 91.227%	pattern: 47	before: 106	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.227%	pattern: 47	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.227%	pattern: 47	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 91.227%	pattern: 47	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.227%	pattern: 47	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 91.227%	pattern: 47	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 91.397%	pattern: 48	before: 103	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 91.397%	pattern: 48	before: 101	now: 101
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 91.908%	pattern: 49	before: 101	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 91.908%	pattern: 49	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 91.908%	pattern: 49	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.908%	pattern: 49	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 91.908%	pattern: 49	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 91.993%	pattern: 50	before: 95	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+coverage: 86.371%	pattern: 18	before: 160	now: 160
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+coverage: 86.371%	pattern: 18	before: 160	now: 160
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 86.371%	pattern: 18	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 86.371%	pattern: 18	before: 160	now: 160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 86.457%	pattern: 19	before: 160	now: 159
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 86.457%	pattern: 19	before: 159	now: 159
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 86.457%	pattern: 19	before: 159	now: 159
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 86.712%	pattern: 20	before: 159	now: 156
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 86.882%	pattern: 21	before: 156	now: 154
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+coverage: 86.882%	pattern: 21	before: 154	now: 154
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 87.394%	pattern: 22	before: 154	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 88.075%	pattern: 23	before: 148	now: 140
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+coverage: 88.075%	pattern: 23	before: 140	now: 140
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+coverage: 88.075%	pattern: 23	before: 140	now: 140
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 88.330%	pattern: 24	before: 140	now: 137
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 88.416%	pattern: 25	before: 137	now: 136
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 91.993%	pattern: 50	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 92.164%	pattern: 51	before: 94	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 88.416%	pattern: 25	before: 136	now: 136
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 88.416%	pattern: 25	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 88.501%	pattern: 26	before: 136	now: 135
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 88.501%	pattern: 26	before: 135	now: 135
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 88.501%	pattern: 26	before: 135	now: 135
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 88.501%	pattern: 26	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 88.501%	pattern: 26	before: 135	now: 135
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 88.501%	pattern: 26	before: 135	now: 135
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 88.501%	pattern: 26	before: 135	now: 135
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 88.501%	pattern: 26	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 89.182%	pattern: 27	before: 135	now: 127
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 89.353%	pattern: 28	before: 127	now: 125
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 89.864%	pattern: 29	before: 125	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 89.864%	pattern: 29	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.864%	pattern: 29	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 89.864%	pattern: 29	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
+coverage: 89.864%	pattern: 29	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.864%	pattern: 29	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 92.164%	pattern: 51	before: 92	now: 92
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 92.249%	pattern: 52	before: 92	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 92.249%	pattern: 52	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 92.675%	pattern: 53	before: 91	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 92.675%	pattern: 53	before: 86	now: 86
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 92.845%	pattern: 54	before: 86	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 92.845%	pattern: 54	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 92.845%	pattern: 54	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 92.845%	pattern: 54	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.845%	pattern: 54	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 92.845%	pattern: 54	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 92.845%	pattern: 54	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 92.845%	pattern: 54	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 92.845%	pattern: 54	before: 84	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 93.356%	pattern: 55	before: 84	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 93.356%	pattern: 55	before: 78	now: 78
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.356%	pattern: 55	before: 78	now: 78
+coverage: 89.864%	pattern: 29	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 93.356%	pattern: 55	before: 78	now: 78
+coverage: 89.864%	pattern: 29	before: 119	now: 119
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 93.356%	pattern: 55	before: 78	now: 78
+coverage: 89.864%	pattern: 29	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.864%	pattern: 29	before: 119	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 89.949%	pattern: 30	before: 119	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.949%	pattern: 30	before: 118	now: 118
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
+coverage: 89.949%	pattern: 30	before: 118	now: 118
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.356%	pattern: 55	before: 78	now: 78
+coverage: 89.949%	pattern: 30	before: 118	now: 118
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.356%	pattern: 55	before: 78	now: 78
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 93.526%	pattern: 56	before: 78	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 93.526%	pattern: 56	before: 76	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 93.526%	pattern: 56	before: 76	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.526%	pattern: 56	before: 76	now: 76
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 89.949%	pattern: 30	before: 118	now: 118
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 93.526%	pattern: 56	before: 76	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.526%	pattern: 56	before: 76	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 93.526%	pattern: 56	before: 76	now: 76
+coverage: 89.949%	pattern: 30	before: 118	now: 118
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.526%	pattern: 56	before: 76	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 93.526%	pattern: 56	before: 76	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 93.526%	pattern: 56	before: 76	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.526%	pattern: 56	before: 76	now: 76
+coverage: 89.949%	pattern: 30	before: 118	now: 118
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 93.526%	pattern: 56	before: 76	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 93.697%	pattern: 57	before: 76	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 93.697%	pattern: 57	before: 74	now: 74
+coverage: 89.949%	pattern: 30	before: 118	now: 118
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.697%	pattern: 57	before: 74	now: 74
+coverage: 89.949%	pattern: 30	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 89.949%	pattern: 30	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 89.949%	pattern: 30	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 90.204%	pattern: 31	before: 118	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 90.204%	pattern: 31	before: 115	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 90.204%	pattern: 31	before: 115	now: 115
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 90.290%	pattern: 32	before: 115	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 93.697%	pattern: 57	before: 74	now: 74
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 93.697%	pattern: 57	before: 74	now: 74
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 94.123%	pattern: 58	before: 74	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.123%	pattern: 58	before: 69	now: 69
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.123%	pattern: 58	before: 69	now: 69
+coverage: 90.290%	pattern: 32	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.123%	pattern: 58	before: 69	now: 69
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.123%	pattern: 58	before: 69	now: 69
+coverage: 90.290%	pattern: 32	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.123%	pattern: 58	before: 69	now: 69
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.123%	pattern: 58	before: 69	now: 69
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.123%	pattern: 58	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 94.123%	pattern: 58	before: 69	now: 69
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 90.290%	pattern: 32	before: 114	now: 114
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 94.293%	pattern: 59	before: 69	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+coverage: 90.460%	pattern: 33	before: 114	now: 112
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+coverage: 90.460%	pattern: 33	before: 112	now: 112
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+coverage: 90.460%	pattern: 33	before: 112	now: 112
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+coverage: 90.460%	pattern: 33	before: 112	now: 112
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+coverage: 90.460%	pattern: 33	before: 112	now: 112
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+coverage: 90.460%	pattern: 33	before: 112	now: 112
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 90.630%	pattern: 34	before: 112	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.293%	pattern: 59	before: 67	now: 67
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 94.293%	pattern: 59	before: 67	now: 67
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 94.804%	pattern: 60	before: 67	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 94.804%	pattern: 60	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 94.974%	pattern: 61	before: 61	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 95.145%	pattern: 62	before: 59	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.145%	pattern: 62	before: 57	now: 57
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 95.315%	pattern: 63	before: 57	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.315%	pattern: 63	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 95.400%	pattern: 64	before: 55	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.400%	pattern: 64	before: 54	now: 54
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 95.571%	pattern: 65	before: 54	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.571%	pattern: 65	before: 52	now: 52
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 95.656%	pattern: 66	before: 52	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.656%	pattern: 66	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 95.826%	pattern: 67	before: 51	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.826%	pattern: 67	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 95.911%	pattern: 68	before: 49	now: 48
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.911%	pattern: 68	before: 48	now: 48
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.911%	pattern: 68	before: 48	now: 48
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 95.911%	pattern: 68	before: 48	now: 48
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 95.911%	pattern: 68	before: 48	now: 48
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 95.911%	pattern: 68	before: 48	now: 48
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 95.997%	pattern: 69	before: 48	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 95.997%	pattern: 69	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 96.167%	pattern: 70	before: 47	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+coverage: 90.630%	pattern: 34	before: 110	now: 110
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.167%	pattern: 70	before: 45	now: 45
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 96.252%	pattern: 71	before: 45	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.252%	pattern: 71	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.252%	pattern: 71	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.252%	pattern: 71	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.252%	pattern: 71	before: 44	now: 44
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 96.337%	pattern: 72	before: 44	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 96.337%	pattern: 72	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 96.422%	pattern: 73	before: 43	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 96.422%	pattern: 73	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 96.508%	pattern: 74	before: 42	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:344
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.508%	pattern: 74	before: 41	now: 41
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 96.593%	pattern: 75	before: 41	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 96.593%	pattern: 75	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 96.763%	pattern: 76	before: 40	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 96.763%	pattern: 76	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 96.934%	pattern: 77	before: 38	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 96.934%	pattern: 77	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 97.019%	pattern: 78	before: 36	now: 35
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 97.019%	pattern: 78	before: 35	now: 35
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 97.189%	pattern: 79	before: 35	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.189%	pattern: 79	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 97.359%	pattern: 80	before: 33	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.359%	pattern: 80	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 97.445%	pattern: 81	before: 31	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.445%	pattern: 81	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 97.615%	pattern: 82	before: 30	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.615%	pattern: 82	before: 28	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 97.785%	pattern: 83	before: 28	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 97.785%	pattern: 83	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 97.871%	pattern: 84	before: 26	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 97.871%	pattern: 84	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 98.041%	pattern: 85	before: 25	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.041%	pattern: 85	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.126%	pattern: 86	before: 23	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.126%	pattern: 86	before: 22	now: 22
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 98.211%	pattern: 87	before: 22	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.211%	pattern: 87	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 98.382%	pattern: 88	before: 21	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.382%	pattern: 88	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 98.552%	pattern: 89	before: 19	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.552%	pattern: 89	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.637%	pattern: 90	before: 17	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.637%	pattern: 90	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 98.722%	pattern: 91	before: 16	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.722%	pattern: 91	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.807%	pattern: 92	before: 15	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.807%	pattern: 92	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.893%	pattern: 93	before: 14	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.893%	pattern: 93	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 98.978%	pattern: 94	before: 13	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 98.978%	pattern: 94	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.063%	pattern: 95	before: 12	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.063%	pattern: 95	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.148%	pattern: 96	before: 11	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.148%	pattern: 96	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.233%	pattern: 97	before: 10	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.233%	pattern: 97	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.319%	pattern: 98	before: 9	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.319%	pattern: 98	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.404%	pattern: 99	before: 8	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.404%	pattern: 99	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.489%	pattern: 100	before: 7	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.489%	pattern: 100	before: 6	now: 6
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.489%	pattern: 100	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.574%	pattern: 101	before: 6	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 90.630%	pattern: 34	before: 110	now: 110
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 90.801%	pattern: 35	before: 110	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 90.801%	pattern: 35	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 90.801%	pattern: 35	before: 108	now: 108
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 90.801%	pattern: 35	before: 108	now: 108
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 90.801%	pattern: 35	before: 108	now: 108
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 91.227%	pattern: 36	before: 108	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 91.227%	pattern: 36	before: 103	now: 103
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:371
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.574%	pattern: 101	before: 5	now: 5
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.574%	pattern: 101	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 99.659%	pattern: 102	before: 5	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.659%	pattern: 102	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.744%	pattern: 103	before: 4	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.227%	pattern: 36	before: 103	now: 103
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 91.397%	pattern: 37	before: 103	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 91.397%	pattern: 37	before: 101	now: 101
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 91.397%	pattern: 37	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 91.397%	pattern: 37	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 91.397%	pattern: 37	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 91.397%	pattern: 37	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:464
+coverage: 91.908%	pattern: 38	before: 101	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:292
+coverage: 91.908%	pattern: 38	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 91.908%	pattern: 38	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 91.908%	pattern: 38	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 91.908%	pattern: 38	before: 95	now: 95
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 91.908%	pattern: 38	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 92.675%	pattern: 39	before: 95	now: 86
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 92.675%	pattern: 39	before: 86	now: 86
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 92.675%	pattern: 39	before: 86	now: 86
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 92.675%	pattern: 39	before: 86	now: 86
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 92.675%	pattern: 39	before: 86	now: 86
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 93.101%	pattern: 40	before: 86	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.101%	pattern: 40	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 93.101%	pattern: 40	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 93.101%	pattern: 40	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 93.101%	pattern: 40	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.101%	pattern: 40	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 93.101%	pattern: 40	before: 81	now: 81
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.101%	pattern: 40	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 93.101%	pattern: 40	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 93.526%	pattern: 41	before: 81	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
-coverage: 99.744%	pattern: 103	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
-coverage: 99.744%	pattern: 103	before: 3	now: 3
+coverage: 93.526%	pattern: 41	before: 76	now: 76
 checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 93.526%	pattern: 41	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 93.697%	pattern: 42	before: 76	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 93.697%	pattern: 42	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 93.697%	pattern: 42	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 93.697%	pattern: 42	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 93.697%	pattern: 42	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 93.697%	pattern: 42	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 93.867%	pattern: 43	before: 74	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 93.867%	pattern: 43	before: 72	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 94.037%	pattern: 44	before: 72	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.037%	pattern: 44	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 94.123%	pattern: 45	before: 70	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 94.123%	pattern: 45	before: 69	now: 69
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
+coverage: 94.293%	pattern: 46	before: 69	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 94.293%	pattern: 46	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 94.804%	pattern: 47	before: 67	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.804%	pattern: 47	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 94.804%	pattern: 47	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 94.804%	pattern: 47	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.804%	pattern: 47	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.804%	pattern: 47	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 94.974%	pattern: 48	before: 61	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 94.974%	pattern: 48	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 95.145%	pattern: 49	before: 59	now: 57
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 95.145%	pattern: 49	before: 57	now: 57
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 95.315%	pattern: 50	before: 57	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.315%	pattern: 50	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.315%	pattern: 50	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 95.400%	pattern: 51	before: 55	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.400%	pattern: 51	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 95.571%	pattern: 52	before: 54	now: 52
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 95.571%	pattern: 52	before: 52	now: 52
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 95.571%	pattern: 52	before: 52	now: 52
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 95.741%	pattern: 53	before: 52	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.741%	pattern: 53	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:461
+coverage: 95.911%	pattern: 54	before: 50	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 95.911%	pattern: 54	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 96.082%	pattern: 55	before: 48	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.082%	pattern: 55	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.082%	pattern: 55	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.082%	pattern: 55	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.082%	pattern: 55	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.082%	pattern: 55	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:462
+coverage: 96.167%	pattern: 56	before: 46	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 96.167%	pattern: 56	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 96.252%	pattern: 57	before: 45	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.252%	pattern: 57	before: 44	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.252%	pattern: 57	before: 44	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.252%	pattern: 57	before: 44	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 96.252%	pattern: 57	before: 44	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.252%	pattern: 57	before: 44	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.252%	pattern: 57	before: 44	now: 44
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 96.422%	pattern: 58	before: 44	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:463
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.422%	pattern: 58	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 96.593%	pattern: 59	before: 42	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.593%	pattern: 59	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 96.763%	pattern: 60	before: 40	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 96.763%	pattern: 60	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.763%	pattern: 60	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 96.934%	pattern: 61	before: 38	now: 36
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.934%	pattern: 61	before: 36	now: 36
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 96.934%	pattern: 61	before: 36	now: 36
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 96.934%	pattern: 61	before: 36	now: 36
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 96.934%	pattern: 61	before: 36	now: 36
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 96.934%	pattern: 61	before: 36	now: 36
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 97.019%	pattern: 62	before: 36	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.019%	pattern: 62	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:292
+coverage: 97.019%	pattern: 62	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.019%	pattern: 62	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.019%	pattern: 62	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.019%	pattern: 62	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
+coverage: 97.019%	pattern: 62	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 97.104%	pattern: 63	before: 35	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.104%	pattern: 63	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.104%	pattern: 63	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.104%	pattern: 63	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 97.274%	pattern: 64	before: 34	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 97.274%	pattern: 64	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 97.274%	pattern: 64	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.274%	pattern: 64	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.274%	pattern: 64	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 97.274%	pattern: 64	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 97.274%	pattern: 64	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 97.274%	pattern: 64	before: 32	now: 32
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 97.359%	pattern: 65	before: 32	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 97.445%	pattern: 66	before: 31	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 97.445%	pattern: 66	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 97.530%	pattern: 67	before: 30	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.530%	pattern: 67	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:462
+coverage: 97.615%	pattern: 68	before: 29	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.615%	pattern: 68	before: 28	now: 28
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 97.700%	pattern: 69	before: 28	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 97.785%	pattern: 70	before: 27	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.785%	pattern: 70	before: 26	now: 26
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 97.871%	pattern: 71	before: 26	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 97.871%	pattern: 71	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 97.956%	pattern: 72	before: 25	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 97.956%	pattern: 72	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 97.956%	pattern: 72	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 97.956%	pattern: 72	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 98.041%	pattern: 73	before: 24	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 98.041%	pattern: 73	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:462
+coverage: 98.126%	pattern: 74	before: 23	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.126%	pattern: 74	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 98.126%	pattern: 74	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 98.211%	pattern: 75	before: 22	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.211%	pattern: 75	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 98.296%	pattern: 76	before: 21	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 98.296%	pattern: 76	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 98.467%	pattern: 77	before: 20	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 98.467%	pattern: 77	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 98.637%	pattern: 78	before: 18	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 98.637%	pattern: 78	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 98.722%	pattern: 79	before: 16	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.722%	pattern: 79	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 98.807%	pattern: 80	before: 15	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 98.807%	pattern: 80	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 98.893%	pattern: 81	before: 14	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.893%	pattern: 81	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 98.978%	pattern: 82	before: 13	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 98.978%	pattern: 82	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 99.063%	pattern: 83	before: 12	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.063%	pattern: 83	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.148%	pattern: 84	before: 11	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:465
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:372
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.148%	pattern: 84	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.233%	pattern: 85	before: 10	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.233%	pattern: 85	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.319%	pattern: 86	before: 9	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.319%	pattern: 86	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.319%	pattern: 86	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.319%	pattern: 86	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.404%	pattern: 87	before: 8	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:463
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.404%	pattern: 87	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.574%	pattern: 88	before: 7	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.574%	pattern: 88	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.659%	pattern: 89	before: 5	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:465
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:461
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:461
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.659%	pattern: 89	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.744%	pattern: 90	before: 4	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:292
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:463
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.744%	pattern: 90	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.830%	pattern: 91	before: 3	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:461
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:461
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:464
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:463
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.830%	pattern: 91	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.915%	pattern: 92	before: 2	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:370
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:461
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:369
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:463
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:368
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:461
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:456
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:461
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:371
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:459
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:458
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:460
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196
+coverage: 99.915%	pattern: 92	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:453
+coverage: 100.000%	pattern: 93	before: 1	now: 0
+checking valid circuit ... result: 1.
+
+real	5m54.878s
+user	5m54.850s
+sys	0m0.016s
diff --git a/exp_result/ATPG-LS_c17.bench.txt b/exp_result/ATPG-LS_c17.bench.txt
index db95724..4937c6f 100644
--- a/exp_result/ATPG-LS_c17.bench.txt
+++ b/exp_result/ATPG-LS_c17.bench.txt
@@ -20,10 +20,10 @@ checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 9, fault_cnt:8
 coverage: 90.909%	pattern: 3	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 9, fault_cnt:6
+[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 9, fault_cnt:5
 coverage: 100.000%	pattern: 4	before: 2	now: 0
 checking valid circuit ... result: 1.
 
-real	0m0.004s
+real	0m0.003s
 user	0m0.002s
 sys	0m0.000s
diff --git a/exp_result/ATPG-LS_c1908.bench.txt b/exp_result/ATPG-LS_c1908.bench.txt
index fe1d7b0..6bc947d 100644
--- a/exp_result/ATPG-LS_c1908.bench.txt
+++ b/exp_result/ATPG-LS_c1908.bench.txt
@@ -8,7662 +8,18366 @@ Gate:	913
 Stem:	410
 Level:	12
 ================================ 
-[SOL] flip: 0, stem: 0, fault:9429. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 27.273%	pattern: 1	before: 1826	now: 1328
+[SOL] flip: 0, stem: 0, fault:9294. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 27.820%	pattern: 1	before: 1826	now: 1318
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5572. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
-coverage: 46.440%	pattern: 2	before: 1328	now: 978
+[SOL] flip: 0, stem: 0, fault:3231. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 38.171%	pattern: 2	before: 1318	now: 1129
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2452. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 53.560%	pattern: 3	before: 978	now: 848
+[SOL] flip: 0, stem: 0, fault:372. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 39.266%	pattern: 3	before: 1129	now: 1109
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 54.819%	pattern: 4	before: 848	now: 825
+[SOL] flip: 0, stem: 0, fault:3576. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 49.617%	pattern: 4	before: 1109	now: 920
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1235. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 58.379%	pattern: 5	before: 825	now: 760
+[SOL] flip: 0, stem: 0, fault:2204. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
+coverage: 55.969%	pattern: 5	before: 920	now: 804
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 58.817%	pattern: 6	before: 760	now: 752
+[SOL] flip: 0, stem: 0, fault:1482. flip_cnt: 0, stem_cnt: 410, fault_cnt:542
+coverage: 60.241%	pattern: 6	before: 804	now: 726
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:836. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 61.227%	pattern: 7	before: 752	now: 708
+[SOL] flip: 0, stem: 0, fault:116. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 60.679%	pattern: 7	before: 726	now: 718
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 410, fault_cnt:567
-coverage: 64.239%	pattern: 8	before: 708	now: 653
+[SOL] flip: 0, stem: 0, fault:570. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 62.322%	pattern: 8	before: 718	now: 688
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:343. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 65.279%	pattern: 9	before: 653	now: 634
+[SOL] flip: 0, stem: 0, fault:3533. flip_cnt: 0, stem_cnt: 410, fault_cnt:649
+coverage: 72.563%	pattern: 9	before: 688	now: 501
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
-coverage: 65.717%	pattern: 10	before: 634	now: 626
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 73.111%	pattern: 10	before: 501	now: 491
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
-coverage: 65.882%	pattern: 11	before: 626	now: 623
+[SOL] flip: 0, stem: 0, fault:233. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 73.877%	pattern: 11	before: 491	now: 477
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 66.101%	pattern: 12	before: 623	now: 619
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 74.261%	pattern: 12	before: 477	now: 470
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 66.320%	pattern: 13	before: 619	now: 615
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 74.480%	pattern: 13	before: 470	now: 466
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 66.539%	pattern: 14	before: 615	now: 611
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 66.594%	pattern: 15	before: 611	now: 610
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 66.703%	pattern: 16	before: 610	now: 608
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 66.703%	pattern: 16	before: 608	now: 608
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 66.813%	pattern: 17	before: 608	now: 606
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 66.813%	pattern: 17	before: 606	now: 606
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
-coverage: 67.032%	pattern: 18	before: 606	now: 602
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 67.032%	pattern: 18	before: 602	now: 602
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 67.032%	pattern: 18	before: 602	now: 602
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 67.251%	pattern: 19	before: 602	now: 598
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
-coverage: 67.251%	pattern: 19	before: 598	now: 598
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
-coverage: 67.251%	pattern: 19	before: 598	now: 598
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
-coverage: 67.251%	pattern: 19	before: 598	now: 598
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2736. flip_cnt: 0, stem_cnt: 410, fault_cnt:640
-coverage: 75.137%	pattern: 20	before: 598	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
-coverage: 75.137%	pattern: 20	before: 454	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 75.137%	pattern: 20	before: 454	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 75.137%	pattern: 20	before: 454	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 75.137%	pattern: 20	before: 454	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 75.246%	pattern: 21	before: 454	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
-coverage: 75.246%	pattern: 21	before: 452	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 75.246%	pattern: 21	before: 452	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 75.246%	pattern: 21	before: 452	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 75.246%	pattern: 21	before: 452	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 75.246%	pattern: 21	before: 452	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 75.465%	pattern: 22	before: 452	now: 448
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 75.465%	pattern: 22	before: 448	now: 448
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 75.520%	pattern: 23	before: 448	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 75.520%	pattern: 23	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 410, fault_cnt:172
-coverage: 76.616%	pattern: 24	before: 447	now: 427
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 74.918%	pattern: 14	before: 466	now: 458
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 76.616%	pattern: 24	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 76.616%	pattern: 24	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 76.616%	pattern: 24	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 76.616%	pattern: 24	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 76.616%	pattern: 24	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 76.616%	pattern: 24	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 76.670%	pattern: 25	before: 427	now: 426
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 76.670%	pattern: 25	before: 426	now: 426
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 76.670%	pattern: 25	before: 426	now: 426
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 76.670%	pattern: 25	before: 426	now: 426
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 76.670%	pattern: 25	before: 426	now: 426
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 76.670%	pattern: 25	before: 426	now: 426
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 410, fault_cnt:658
-coverage: 79.409%	pattern: 26	before: 426	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 79.409%	pattern: 26	before: 376	now: 376
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 79.518%	pattern: 27	before: 376	now: 374
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 410, fault_cnt:540
-coverage: 80.504%	pattern: 28	before: 374	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 80.504%	pattern: 28	before: 356	now: 356
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 80.559%	pattern: 29	before: 356	now: 355
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 80.559%	pattern: 29	before: 355	now: 355
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 80.559%	pattern: 29	before: 355	now: 355
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 80.559%	pattern: 29	before: 355	now: 355
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 410, fault_cnt:628
-coverage: 83.352%	pattern: 30	before: 355	now: 304
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 83.352%	pattern: 30	before: 304	now: 304
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 83.680%	pattern: 31	before: 304	now: 298
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
-coverage: 83.680%	pattern: 31	before: 298	now: 298
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 410, fault_cnt:629
-coverage: 84.666%	pattern: 32	before: 298	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
-coverage: 84.666%	pattern: 32	before: 280	now: 280
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 85.049%	pattern: 33	before: 280	now: 273
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 85.049%	pattern: 33	before: 273	now: 273
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 85.049%	pattern: 33	before: 273	now: 273
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 85.049%	pattern: 33	before: 273	now: 273
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:557
-coverage: 85.104%	pattern: 34	before: 273	now: 272
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 85.104%	pattern: 34	before: 272	now: 272
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 85.104%	pattern: 34	before: 272	now: 272
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
-coverage: 85.159%	pattern: 35	before: 272	now: 271
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 85.159%	pattern: 35	before: 271	now: 271
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 85.487%	pattern: 36	before: 271	now: 265
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 410, fault_cnt:595
-coverage: 85.761%	pattern: 37	before: 265	now: 260
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 85.761%	pattern: 37	before: 260	now: 260
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 85.761%	pattern: 37	before: 260	now: 260
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 85.761%	pattern: 37	before: 260	now: 260
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
-coverage: 85.761%	pattern: 37	before: 260	now: 260
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 85.761%	pattern: 37	before: 260	now: 260
+coverage: 74.918%	pattern: 14	before: 458	now: 458
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
-coverage: 85.761%	pattern: 37	before: 260	now: 260
+coverage: 74.918%	pattern: 14	before: 458	now: 458
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 85.761%	pattern: 37	before: 260	now: 260
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 74.918%	pattern: 14	before: 458	now: 458
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:538
-coverage: 85.871%	pattern: 38	before: 260	now: 258
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:438
+coverage: 75.246%	pattern: 15	before: 458	now: 452
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 85.871%	pattern: 38	before: 258	now: 258
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 75.520%	pattern: 16	before: 452	now: 447
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 410, fault_cnt:651
-coverage: 88.445%	pattern: 39	before: 258	now: 211
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 75.630%	pattern: 17	before: 447	now: 445
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:556
-coverage: 88.664%	pattern: 40	before: 211	now: 207
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 75.630%	pattern: 17	before: 445	now: 445
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 88.664%	pattern: 40	before: 207	now: 207
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 75.630%	pattern: 17	before: 445	now: 445
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 88.664%	pattern: 40	before: 207	now: 207
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 75.630%	pattern: 17	before: 445	now: 445
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 88.664%	pattern: 40	before: 207	now: 207
+[SOL] flip: 0, stem: 0, fault:1425. flip_cnt: 0, stem_cnt: 410, fault_cnt:641
+coverage: 79.737%	pattern: 18	before: 445	now: 370
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 88.664%	pattern: 40	before: 207	now: 207
+[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 410, fault_cnt:221
+coverage: 80.559%	pattern: 19	before: 370	now: 355
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 88.664%	pattern: 40	before: 207	now: 207
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 80.668%	pattern: 20	before: 355	now: 353
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
-coverage: 88.664%	pattern: 40	before: 207	now: 207
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 80.668%	pattern: 20	before: 353	now: 353
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:567
-coverage: 88.883%	pattern: 41	before: 207	now: 203
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 80.778%	pattern: 21	before: 353	now: 351
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 88.883%	pattern: 41	before: 203	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
-coverage: 88.883%	pattern: 41	before: 203	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 88.883%	pattern: 41	before: 203	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 88.883%	pattern: 41	before: 203	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
-coverage: 88.883%	pattern: 41	before: 203	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 88.883%	pattern: 41	before: 203	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 88.883%	pattern: 41	before: 203	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 88.883%	pattern: 41	before: 203	now: 203
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:582
-coverage: 88.992%	pattern: 42	before: 203	now: 201
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 88.992%	pattern: 42	before: 201	now: 201
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 88.992%	pattern: 42	before: 201	now: 201
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
-coverage: 88.992%	pattern: 42	before: 201	now: 201
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 88.992%	pattern: 42	before: 201	now: 201
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:248
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 88.992%	pattern: 42	before: 201	now: 201
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 88.992%	pattern: 42	before: 201	now: 201
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 80.778%	pattern: 21	before: 351	now: 351
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
-coverage: 88.992%	pattern: 42	before: 201	now: 201
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:542
-coverage: 88.992%	pattern: 42	before: 201	now: 201
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:220
-coverage: 89.430%	pattern: 43	before: 201	now: 193
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 89.430%	pattern: 43	before: 193	now: 193
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 89.430%	pattern: 43	before: 193	now: 193
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
-coverage: 89.595%	pattern: 44	before: 193	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
-coverage: 89.595%	pattern: 44	before: 190	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 89.595%	pattern: 44	before: 190	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 89.595%	pattern: 44	before: 190	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:589
-coverage: 89.704%	pattern: 45	before: 190	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 89.704%	pattern: 45	before: 188	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:227
-coverage: 89.704%	pattern: 45	before: 188	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 89.704%	pattern: 45	before: 188	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 89.704%	pattern: 45	before: 188	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 89.704%	pattern: 45	before: 188	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 89.704%	pattern: 45	before: 188	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 89.704%	pattern: 45	before: 188	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 89.704%	pattern: 45	before: 188	now: 188
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 410, fault_cnt:623
-coverage: 90.307%	pattern: 46	before: 188	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
-coverage: 90.307%	pattern: 46	before: 177	now: 177
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 410, fault_cnt:549
-coverage: 91.512%	pattern: 47	before: 177	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 91.512%	pattern: 47	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:566
-coverage: 91.512%	pattern: 47	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 91.512%	pattern: 47	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 91.512%	pattern: 47	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 91.512%	pattern: 47	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 91.512%	pattern: 47	before: 155	now: 155
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 91.731%	pattern: 48	before: 155	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
-coverage: 91.731%	pattern: 48	before: 151	now: 151
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
-coverage: 91.785%	pattern: 49	before: 151	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:592
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 91.785%	pattern: 49	before: 150	now: 150
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 91.785%	pattern: 49	before: 150	now: 150
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:421. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
-coverage: 93.154%	pattern: 50	before: 150	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:590
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 93.154%	pattern: 50	before: 125	now: 125
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:438
-coverage: 93.154%	pattern: 50	before: 125	now: 125
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
-coverage: 93.209%	pattern: 51	before: 125	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 93.209%	pattern: 51	before: 124	now: 124
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:563
-coverage: 93.373%	pattern: 52	before: 124	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
-coverage: 93.373%	pattern: 52	before: 121	now: 121
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 93.373%	pattern: 52	before: 121	now: 121
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:621
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:649
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 93.373%	pattern: 52	before: 121	now: 121
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:617
-coverage: 93.593%	pattern: 53	before: 121	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 93.593%	pattern: 53	before: 117	now: 117
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 93.593%	pattern: 53	before: 117	now: 117
+coverage: 80.778%	pattern: 21	before: 351	now: 351
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:599
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 93.593%	pattern: 53	before: 117	now: 117
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:596
-coverage: 93.757%	pattern: 54	before: 117	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:645
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:206
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:225
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 93.757%	pattern: 54	before: 114	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 93.866%	pattern: 55	before: 114	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 93.866%	pattern: 55	before: 112	now: 112
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 94.031%	pattern: 56	before: 112	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 94.031%	pattern: 56	before: 109	now: 109
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:176
-coverage: 94.085%	pattern: 57	before: 109	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 94.085%	pattern: 57	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579
-coverage: 94.085%	pattern: 57	before: 108	now: 108
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:633
-coverage: 94.140%	pattern: 58	before: 108	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:550
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:645
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:595
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:216
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:646
-coverage: 94.140%	pattern: 58	before: 107	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:597
-coverage: 94.359%	pattern: 59	before: 107	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:573
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 94.359%	pattern: 59	before: 103	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:628
-coverage: 94.578%	pattern: 60	before: 103	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:559
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 94.578%	pattern: 60	before: 99	now: 99
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:647
-coverage: 94.797%	pattern: 61	before: 99	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:584
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:128
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:586
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:635
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 94.797%	pattern: 61	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:584
-coverage: 95.016%	pattern: 62	before: 95	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
-coverage: 95.016%	pattern: 62	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 95.016%	pattern: 62	before: 91	now: 91
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
-coverage: 95.235%	pattern: 63	before: 91	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:641
-coverage: 95.235%	pattern: 63	before: 87	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 95.235%	pattern: 63	before: 87	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:630
-coverage: 95.235%	pattern: 63	before: 87	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 95.235%	pattern: 63	before: 87	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 95.235%	pattern: 63	before: 87	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 95.235%	pattern: 63	before: 87	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:608
-coverage: 95.235%	pattern: 63	before: 87	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 95.235%	pattern: 63	before: 87	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:642
-coverage: 95.345%	pattern: 64	before: 87	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:600
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:545
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 95.345%	pattern: 64	before: 85	now: 85
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
-coverage: 95.783%	pattern: 65	before: 85	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:583
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 95.783%	pattern: 65	before: 77	now: 77
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 95.838%	pattern: 66	before: 77	now: 76
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
-coverage: 96.057%	pattern: 67	before: 76	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:148
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:656
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:431
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:546
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 96.057%	pattern: 67	before: 72	now: 72
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:548
-coverage: 96.386%	pattern: 68	before: 72	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:562
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
-coverage: 96.386%	pattern: 68	before: 66	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
-coverage: 96.440%	pattern: 69	before: 66	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:209
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:593
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:567
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:558
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:219
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:250
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:646
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:626
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:132
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:624
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:599
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 96.440%	pattern: 69	before: 65	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:633
-coverage: 96.659%	pattern: 70	before: 65	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:628
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:597
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 96.659%	pattern: 70	before: 61	now: 61
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:272
-coverage: 96.824%	pattern: 71	before: 61	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:624
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:551
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:213
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:225
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:552
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:620
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
-coverage: 96.824%	pattern: 71	before: 58	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 96.933%	pattern: 72	before: 58	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 96.933%	pattern: 72	before: 56	now: 56
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:580
-coverage: 96.988%	pattern: 73	before: 56	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 96.988%	pattern: 73	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:587
-coverage: 96.988%	pattern: 73	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 96.988%	pattern: 73	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 96.988%	pattern: 73	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
-coverage: 96.988%	pattern: 73	before: 55	now: 55
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.097%	pattern: 74	before: 55	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.097%	pattern: 74	before: 53	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.207%	pattern: 75	before: 53	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:627
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:632
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:433
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:650
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:541
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:583
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:176
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:544
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:547
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:217
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:651
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:220
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:571
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.207%	pattern: 75	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
-coverage: 97.317%	pattern: 76	before: 51	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:555
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:602
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:574
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
-coverage: 97.317%	pattern: 76	before: 49	now: 49
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:624
-coverage: 97.426%	pattern: 77	before: 49	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 97.426%	pattern: 77	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:164
-coverage: 97.426%	pattern: 77	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.426%	pattern: 77	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 97.426%	pattern: 77	before: 47	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:638
-coverage: 97.645%	pattern: 78	before: 47	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:624
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.645%	pattern: 78	before: 43	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
-coverage: 97.700%	pattern: 79	before: 43	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:211
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:560
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:575
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:575
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:212
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:641
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.700%	pattern: 79	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:271
-coverage: 97.809%	pattern: 80	before: 42	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:538
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:638
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:556
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:553
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:179
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:658
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:652
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:559
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:576
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:549
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:567
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:541
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.809%	pattern: 80	before: 40	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:646
-coverage: 97.919%	pattern: 81	before: 40	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:551
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:582
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:215
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:553
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:552
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:213
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:162
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:586
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:223
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:563
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:201
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:589
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 97.919%	pattern: 81	before: 38	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:644
-coverage: 98.028%	pattern: 82	before: 38	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:601
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:640
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:583
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:543
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:594
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:587
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:541
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:565
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:166
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:629
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:221
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:431
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 98.028%	pattern: 82	before: 36	now: 36
+[SOL] flip: 0, stem: 0, fault:912. flip_cnt: 0, stem_cnt: 410, fault_cnt:624
+coverage: 83.406%	pattern: 22	before: 351	now: 303
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:210
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:547
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 98.028%	pattern: 82	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:222
-coverage: 98.138%	pattern: 83	before: 36	now: 34
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 98.138%	pattern: 83	before: 34	now: 34
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:631
-coverage: 98.193%	pattern: 84	before: 34	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:641
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.193%	pattern: 84	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:573
-coverage: 98.302%	pattern: 85	before: 33	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
-coverage: 98.302%	pattern: 85	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
-coverage: 98.302%	pattern: 85	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 98.302%	pattern: 85	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.302%	pattern: 85	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 98.302%	pattern: 85	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 98.302%	pattern: 85	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 98.302%	pattern: 85	before: 31	now: 31
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:645
-coverage: 98.412%	pattern: 86	before: 31	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:636
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:577
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:565
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:632
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:250
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:638
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:164
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 98.412%	pattern: 86	before: 29	now: 29
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:541
-coverage: 98.576%	pattern: 87	before: 29	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:213
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:652
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:549
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:223
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:589
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:438
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 98.576%	pattern: 87	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:270
-coverage: 98.740%	pattern: 88	before: 26	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:550
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:577
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:578
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:560
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 98.740%	pattern: 88	before: 23	now: 23
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:563
-coverage: 98.850%	pattern: 89	before: 23	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:649
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:622
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:593
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:542
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:630
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:626
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 98.850%	pattern: 89	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:622
-coverage: 99.069%	pattern: 90	before: 21	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:150
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:639
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:610
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:609
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:652
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:556
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:558
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:574
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:222
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:546
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:640
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 99.069%	pattern: 90	before: 17	now: 17
+coverage: 83.406%	pattern: 22	before: 303	now: 303
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
-coverage: 99.069%	pattern: 90	before: 17	now: 17
+coverage: 83.406%	pattern: 22	before: 303	now: 303
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:218
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:564
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:581
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:549
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:557
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:571
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
-coverage: 99.069%	pattern: 90	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
-coverage: 99.069%	pattern: 90	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 83.406%	pattern: 22	before: 303	now: 303
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
-coverage: 99.069%	pattern: 90	before: 17	now: 17
+coverage: 83.406%	pattern: 22	before: 303	now: 303
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
-coverage: 99.069%	pattern: 90	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 83.406%	pattern: 22	before: 303	now: 303
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 99.069%	pattern: 90	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 83.406%	pattern: 22	before: 303	now: 303
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:640
-coverage: 99.179%	pattern: 91	before: 17	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 83.406%	pattern: 22	before: 303	now: 303
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:722. flip_cnt: 0, stem_cnt: 410, fault_cnt:586
+coverage: 85.487%	pattern: 23	before: 303	now: 265
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 85.597%	pattern: 24	before: 265	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 85.597%	pattern: 24	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 85.597%	pattern: 24	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 85.597%	pattern: 24	before: 263	now: 263
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+coverage: 85.597%	pattern: 24	before: 263	now: 263
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
+coverage: 85.652%	pattern: 25	before: 263	now: 262
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 85.652%	pattern: 25	before: 262	now: 262
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 85.706%	pattern: 26	before: 262	now: 261
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 85.926%	pattern: 27	before: 261	now: 257
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 85.926%	pattern: 27	before: 257	now: 257
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 85.926%	pattern: 27	before: 257	now: 257
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 85.926%	pattern: 27	before: 257	now: 257
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 85.926%	pattern: 27	before: 257	now: 257
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 85.926%	pattern: 27	before: 257	now: 257
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 85.926%	pattern: 27	before: 257	now: 257
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:538
+coverage: 86.035%	pattern: 28	before: 257	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
+coverage: 86.035%	pattern: 28	before: 255	now: 255
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+coverage: 86.035%	pattern: 28	before: 255	now: 255
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:221
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 86.035%	pattern: 28	before: 255	now: 255
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:438
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:128
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 86.035%	pattern: 28	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 86.090%	pattern: 29	before: 255	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 86.090%	pattern: 29	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 86.199%	pattern: 30	before: 254	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 86.199%	pattern: 30	before: 252	now: 252
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 86.528%	pattern: 31	before: 252	now: 246
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 86.528%	pattern: 31	before: 246	now: 246
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 86.528%	pattern: 31	before: 246	now: 246
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 86.528%	pattern: 31	before: 246	now: 246
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 86.528%	pattern: 31	before: 246	now: 246
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 86.528%	pattern: 31	before: 246	now: 246
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 86.528%	pattern: 31	before: 246	now: 246
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 86.583%	pattern: 32	before: 246	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 86.583%	pattern: 32	before: 245	now: 245
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 86.583%	pattern: 32	before: 245	now: 245
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+coverage: 86.583%	pattern: 32	before: 245	now: 245
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 86.583%	pattern: 32	before: 245	now: 245
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 86.583%	pattern: 32	before: 245	now: 245
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 86.583%	pattern: 32	before: 245	now: 245
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:128
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 86.583%	pattern: 32	before: 245	now: 245
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 410, fault_cnt:545
+coverage: 87.842%	pattern: 33	before: 245	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 87.842%	pattern: 33	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:988. flip_cnt: 0, stem_cnt: 410, fault_cnt:636
+coverage: 90.690%	pattern: 34	before: 222	now: 170
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
-coverage: 99.179%	pattern: 91	before: 15	now: 15
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 90.690%	pattern: 34	before: 170	now: 170
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:272
+coverage: 90.800%	pattern: 35	before: 170	now: 168
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 90.800%	pattern: 35	before: 168	now: 168
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 90.800%	pattern: 35	before: 168	now: 168
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 90.800%	pattern: 35	before: 168	now: 168
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 410, fault_cnt:645
+coverage: 91.347%	pattern: 36	before: 168	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:179
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:248
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 91.347%	pattern: 36	before: 158	now: 158
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 91.621%	pattern: 37	before: 158	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 91.621%	pattern: 37	before: 153	now: 153
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 410, fault_cnt:594
+coverage: 91.895%	pattern: 38	before: 153	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:431
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:224
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:433
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:438
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
+coverage: 91.895%	pattern: 38	before: 148	now: 148
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 410, fault_cnt:668
+coverage: 92.552%	pattern: 39	before: 148	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 92.552%	pattern: 39	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 92.552%	pattern: 39	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 92.552%	pattern: 39	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 92.552%	pattern: 39	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 92.552%	pattern: 39	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 92.552%	pattern: 39	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:544
+coverage: 92.607%	pattern: 40	before: 136	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:129
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 92.607%	pattern: 40	before: 135	now: 135
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:630
+coverage: 92.826%	pattern: 41	before: 135	now: 131
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 92.826%	pattern: 41	before: 131	now: 131
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 92.826%	pattern: 41	before: 131	now: 131
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 92.826%	pattern: 41	before: 131	now: 131
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 92.826%	pattern: 41	before: 131	now: 131
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:567
+coverage: 93.045%	pattern: 42	before: 131	now: 127
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 93.045%	pattern: 42	before: 127	now: 127
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:540
+coverage: 93.209%	pattern: 43	before: 127	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:219
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 93.209%	pattern: 43	before: 124	now: 124
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:538
+coverage: 93.538%	pattern: 44	before: 124	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:595
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 93.538%	pattern: 44	before: 118	now: 118
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:642
+coverage: 93.757%	pattern: 45	before: 118	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 93.757%	pattern: 45	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
+coverage: 94.085%	pattern: 46	before: 114	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:540
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:558
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:576
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:578
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:248
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:214
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 94.085%	pattern: 46	before: 108	now: 108
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:569
+coverage: 94.250%	pattern: 47	before: 108	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 94.250%	pattern: 47	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 94.250%	pattern: 47	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 94.250%	pattern: 47	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 94.250%	pattern: 47	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 94.250%	pattern: 47	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 94.250%	pattern: 47	before: 105	now: 105
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:581
+coverage: 94.304%	pattern: 48	before: 105	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:635
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:540
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 94.304%	pattern: 48	before: 104	now: 104
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:624
+coverage: 94.469%	pattern: 49	before: 104	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 94.469%	pattern: 49	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.469%	pattern: 49	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 94.469%	pattern: 49	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 94.469%	pattern: 49	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:78. flip_cnt: 0, stem_cnt: 410, fault_cnt:601
+coverage: 94.797%	pattern: 50	before: 101	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:434
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 94.797%	pattern: 50	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 94.907%	pattern: 51	before: 95	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 94.907%	pattern: 51	before: 93	now: 93
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:592
+coverage: 95.016%	pattern: 52	before: 93	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 95.016%	pattern: 52	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 95.235%	pattern: 53	before: 91	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:572
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:436
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:552
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:177
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 95.235%	pattern: 53	before: 87	now: 87
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:651
+coverage: 95.455%	pattern: 54	before: 87	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 95.455%	pattern: 54	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 95.619%	pattern: 55	before: 83	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:545
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 95.619%	pattern: 55	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:642
+coverage: 95.838%	pattern: 56	before: 80	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:566
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 95.838%	pattern: 56	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 95.947%	pattern: 57	before: 76	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 95.947%	pattern: 57	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 96.057%	pattern: 58	before: 74	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 96.057%	pattern: 58	before: 72	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 96.057%	pattern: 58	before: 72	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.057%	pattern: 58	before: 72	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 96.057%	pattern: 58	before: 72	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 96.057%	pattern: 58	before: 72	now: 72
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 96.166%	pattern: 59	before: 72	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
+coverage: 96.166%	pattern: 59	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:587
+coverage: 96.331%	pattern: 60	before: 70	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:219
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:256
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:557
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:434
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:201
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:216
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 96.331%	pattern: 60	before: 67	now: 67
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:219
+coverage: 96.495%	pattern: 61	before: 67	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
+coverage: 96.495%	pattern: 61	before: 64	now: 64
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:596
+coverage: 96.659%	pattern: 62	before: 64	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:637
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 96.659%	pattern: 62	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:589
+coverage: 96.714%	pattern: 63	before: 61	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:215
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:572
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:659
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:543
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:593
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:595
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:201
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:560
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:248
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 96.714%	pattern: 63	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:649
+coverage: 96.769%	pattern: 64	before: 60	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:628
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 96.769%	pattern: 64	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:638
+coverage: 96.988%	pattern: 65	before: 59	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:149
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:544
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:594
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 96.988%	pattern: 65	before: 55	now: 55
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:592
+coverage: 97.043%	pattern: 66	before: 55	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:656
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:266
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:577
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:435
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:555
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:564
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:627
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:221
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:175
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:659
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:586
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.043%	pattern: 66	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:546
+coverage: 97.207%	pattern: 67	before: 54	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.207%	pattern: 67	before: 51	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.207%	pattern: 67	before: 51	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 97.207%	pattern: 67	before: 51	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.207%	pattern: 67	before: 51	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.207%	pattern: 67	before: 51	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:273
+coverage: 97.371%	pattern: 68	before: 51	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:592
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:167
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:160
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:433
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:540
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:156
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:647
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:220
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:166
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:178
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:628
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:618
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:178
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.371%	pattern: 68	before: 48	now: 48
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:273
+coverage: 97.481%	pattern: 69	before: 48	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:584
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:574
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:540
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:642
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:602
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:590
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:651
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:565
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:620
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:201
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.481%	pattern: 69	before: 46	now: 46
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:566
+coverage: 97.700%	pattern: 70	before: 46	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:595
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.700%	pattern: 70	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:588
+coverage: 97.809%	pattern: 71	before: 42	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:575
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 97.809%	pattern: 71	before: 40	now: 40
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:641
+coverage: 97.919%	pattern: 72	before: 40	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:638
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:626
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:208
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:649
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:221
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:628
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:163
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:656
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:228
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:627
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:131
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:606
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:618
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:595
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:215
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:544
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:644
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:669
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:586
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:215
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:166
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:555
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 97.919%	pattern: 72	before: 38	now: 38
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:542
+coverage: 98.138%	pattern: 73	before: 38	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:434
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:431
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:248
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.138%	pattern: 73	before: 34	now: 34
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:584
+coverage: 98.302%	pattern: 74	before: 34	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:149
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:653
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:228
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:576
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:250
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:149
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:248
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:590
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.302%	pattern: 74	before: 31	now: 31
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:650
+coverage: 98.412%	pattern: 75	before: 31	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:564
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:638
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 98.412%	pattern: 75	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:644
+coverage: 98.521%	pattern: 76	before: 29	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:179
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:645
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:161
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:434
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:572
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:541
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:174
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:620
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:538
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:438
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:206
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:248
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:651
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.521%	pattern: 76	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:552
+coverage: 98.631%	pattern: 77	before: 27	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:574
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:659
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:429
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:433
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:432
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:549
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.631%	pattern: 77	before: 25	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:647
+coverage: 98.740%	pattern: 78	before: 25	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:436
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:129
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:544
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:272
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:595
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 98.740%	pattern: 78	before: 23	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:543
+coverage: 98.795%	pattern: 79	before: 23	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:648
+coverage: 98.850%	pattern: 80	before: 22	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:222
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:274
+coverage: 98.850%	pattern: 80	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 410, fault_cnt:547
+coverage: 98.905%	pattern: 81	before: 21	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:228
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:542
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:178
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:590
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:632
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:271
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:547
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 98.905%	pattern: 81	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:642
+coverage: 99.124%	pattern: 82	before: 20	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:558
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:547
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:227
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 99.124%	pattern: 82	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:628
+coverage: 99.233%	pattern: 83	before: 16	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:623
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:576
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:538
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:584
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:650
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:435
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:267
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:228
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:163
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:574
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:553
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:570
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:430
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:587
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:545
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:201
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:220
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:647
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:589
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:179
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:577
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:590
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:555
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:432
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:624
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:647
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:211
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:555
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:646
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:559
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:179
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:436
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:558
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:209
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:227
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:612
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:633
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:581
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:584
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:146
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:429
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:226
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:212
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:652
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:558
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:206
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:624
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:571
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:176
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:552
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:574
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:610
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:229
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:432
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:205
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:179
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:216
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:635
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:146
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:211
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:544
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:538
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.233%	pattern: 83	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
+coverage: 99.343%	pattern: 84	before: 14	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:636
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:551
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:431
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:177
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:222
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:571
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:218
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:146
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:567
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:248
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:221
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:644
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:208
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:160
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:229
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:649
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:427
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:130
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:573
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:612
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:278
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:641
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:534
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:594
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:586
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:130
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:561
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:542
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:629
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.343%	pattern: 84	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:648
+coverage: 99.452%	pattern: 85	before: 12	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:176
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:146
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:582
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:600
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:250
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:438
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:566
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:572
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:589
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:594
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:537
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:656
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:147
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:577
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:632
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:628
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:431
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:538
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:589
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:608
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:224
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:173
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:581
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485
+coverage: 99.452%	pattern: 85	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470
+coverage: 99.452%	pattern: 85	before: 10	now: 10
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_c2670.bench.txt b/exp_result/ATPG-LS_c2670.bench.txt
index f66d219..efa6d2c 100644
--- a/exp_result/ATPG-LS_c2670.bench.txt
+++ b/exp_result/ATPG-LS_c2670.bench.txt
@@ -8,339 +8,13482 @@ Gate:	1426
 Stem:	696
 Level:	12
 ================================ 
-[SOL] flip: 0, stem: 0, fault:13379. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
-coverage: 24.790%	pattern: 1	before: 2852	now: 2145
+[SOL] flip: 0, stem: 0, fault:9705. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 24.088%	pattern: 1	before: 2852	now: 2165
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5187. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
-coverage: 34.362%	pattern: 2	before: 2145	now: 1872
+[SOL] flip: 0, stem: 0, fault:3507. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 33.275%	pattern: 2	before: 2165	now: 1903
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:6579. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
-coverage: 49.649%	pattern: 3	before: 1872	now: 1436
+[SOL] flip: 0, stem: 0, fault:3895. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 41.830%	pattern: 3	before: 1903	now: 1659
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2783. flip_cnt: 0, stem_cnt: 696, fault_cnt:723
-coverage: 55.049%	pattern: 4	before: 1436	now: 1282
+[SOL] flip: 0, stem: 0, fault:4605. flip_cnt: 0, stem_cnt: 696, fault_cnt:770
+coverage: 51.122%	pattern: 4	before: 1659	now: 1394
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1520. flip_cnt: 0, stem_cnt: 696, fault_cnt:739
-coverage: 57.854%	pattern: 5	before: 1282	now: 1202
+[SOL] flip: 0, stem: 0, fault:1103. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 53.682%	pattern: 5	before: 1394	now: 1321
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2871. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
-coverage: 63.359%	pattern: 6	before: 1202	now: 1045
+[SOL] flip: 0, stem: 0, fault:2262. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 58.310%	pattern: 6	before: 1321	now: 1189
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
-coverage: 64.341%	pattern: 7	before: 1045	now: 1017
+[SOL] flip: 0, stem: 0, fault:2837. flip_cnt: 0, stem_cnt: 696, fault_cnt:779
+coverage: 63.885%	pattern: 7	before: 1189	now: 1030
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1444. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
-coverage: 67.006%	pattern: 8	before: 1017	now: 941
+[SOL] flip: 0, stem: 0, fault:1748. flip_cnt: 0, stem_cnt: 696, fault_cnt:813
+coverage: 67.216%	pattern: 8	before: 1030	now: 935
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
-coverage: 67.882%	pattern: 9	before: 941	now: 916
+[SOL] flip: 0, stem: 0, fault:381. flip_cnt: 0, stem_cnt: 696, fault_cnt:683
+coverage: 67.952%	pattern: 9	before: 935	now: 914
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
-coverage: 69.776%	pattern: 10	before: 916	now: 862
+[SOL] flip: 0, stem: 0, fault:694. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 69.355%	pattern: 10	before: 914	now: 874
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
-coverage: 70.161%	pattern: 11	before: 862	now: 851
+[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 696, fault_cnt:741
+coverage: 70.266%	pattern: 11	before: 874	now: 848
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
-coverage: 70.757%	pattern: 12	before: 851	now: 834
+[SOL] flip: 0, stem: 0, fault:610. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 71.424%	pattern: 12	before: 848	now: 815
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:523. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
-coverage: 71.844%	pattern: 13	before: 834	now: 803
+[SOL] flip: 0, stem: 0, fault:229. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 71.879%	pattern: 13	before: 815	now: 802
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:274. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
-coverage: 72.721%	pattern: 14	before: 803	now: 778
+[SOL] flip: 0, stem: 0, fault:172. flip_cnt: 0, stem_cnt: 696, fault_cnt:430
+coverage: 72.300%	pattern: 14	before: 802	now: 790
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
-coverage: 73.107%	pattern: 15	before: 778	now: 767
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 72.405%	pattern: 15	before: 790	now: 787
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
-coverage: 73.633%	pattern: 16	before: 767	now: 752
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
-coverage: 74.053%	pattern: 17	before: 752	now: 740
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
-coverage: 74.509%	pattern: 18	before: 740	now: 727
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:244. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
-coverage: 75.070%	pattern: 19	before: 727	now: 711
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
-coverage: 75.386%	pattern: 20	before: 711	now: 702
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
-coverage: 75.386%	pattern: 20	before: 702	now: 702
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
-coverage: 75.456%	pattern: 21	before: 702	now: 700
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
-coverage: 75.596%	pattern: 22	before: 700	now: 696
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
-coverage: 75.631%	pattern: 23	before: 696	now: 695
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:439
-coverage: 75.631%	pattern: 23	before: 695	now: 695
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
-coverage: 75.842%	pattern: 24	before: 695	now: 689
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
-coverage: 75.982%	pattern: 25	before: 689	now: 685
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
-coverage: 76.297%	pattern: 26	before: 685	now: 676
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
-coverage: 76.928%	pattern: 27	before: 676	now: 658
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
-coverage: 76.928%	pattern: 27	before: 658	now: 658
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:41. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
-coverage: 77.034%	pattern: 28	before: 658	now: 655
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
-coverage: 77.174%	pattern: 29	before: 655	now: 651
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
-coverage: 77.174%	pattern: 29	before: 651	now: 651
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
-coverage: 77.174%	pattern: 29	before: 651	now: 651
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
-coverage: 77.244%	pattern: 30	before: 651	now: 649
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
-coverage: 77.244%	pattern: 30	before: 649	now: 649
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
-coverage: 77.840%	pattern: 31	before: 649	now: 632
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
-coverage: 77.840%	pattern: 31	before: 632	now: 632
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
-coverage: 77.840%	pattern: 31	before: 632	now: 632
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
-coverage: 77.910%	pattern: 32	before: 632	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
-coverage: 77.910%	pattern: 32	before: 630	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
-coverage: 77.910%	pattern: 32	before: 630	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
-coverage: 77.910%	pattern: 32	before: 630	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
-coverage: 77.910%	pattern: 32	before: 630	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
-coverage: 77.910%	pattern: 32	before: 630	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
-coverage: 77.910%	pattern: 32	before: 630	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:476
-coverage: 77.910%	pattern: 32	before: 630	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
-coverage: 77.910%	pattern: 32	before: 630	now: 630
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
-coverage: 78.647%	pattern: 33	before: 630	now: 609
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
-coverage: 78.647%	pattern: 33	before: 609	now: 609
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
-coverage: 78.647%	pattern: 33	before: 609	now: 609
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:438
-coverage: 78.647%	pattern: 33	before: 609	now: 609
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
-coverage: 78.857%	pattern: 34	before: 609	now: 603
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
-coverage: 78.892%	pattern: 35	before: 603	now: 602
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
-coverage: 78.962%	pattern: 36	before: 602	now: 600
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
-coverage: 79.839%	pattern: 37	before: 600	now: 575
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
-coverage: 79.839%	pattern: 37	before: 575	now: 575
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
-coverage: 79.874%	pattern: 38	before: 575	now: 574
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 696, fault_cnt:756
-coverage: 80.435%	pattern: 39	before: 574	now: 558
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
-coverage: 80.435%	pattern: 39	before: 558	now: 558
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:771
-coverage: 80.505%	pattern: 40	before: 558	now: 556
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
-coverage: 80.540%	pattern: 41	before: 556	now: 555
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
-coverage: 80.540%	pattern: 41	before: 555	now: 555
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
-coverage: 80.540%	pattern: 41	before: 555	now: 555
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
-coverage: 80.540%	pattern: 41	before: 555	now: 555
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
-coverage: 80.610%	pattern: 42	before: 555	now: 553
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
-coverage: 80.891%	pattern: 43	before: 553	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
-coverage: 80.891%	pattern: 43	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
-coverage: 81.171%	pattern: 44	before: 545	now: 537
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
-coverage: 81.206%	pattern: 45	before: 537	now: 536
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
-coverage: 81.241%	pattern: 46	before: 536	now: 535
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
-coverage: 81.241%	pattern: 46	before: 535	now: 535
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
-coverage: 81.452%	pattern: 47	before: 535	now: 529
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:698
-coverage: 81.452%	pattern: 47	before: 529	now: 529
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
-coverage: 81.452%	pattern: 47	before: 529	now: 529
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
-coverage: 81.487%	pattern: 48	before: 529	now: 528
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
-coverage: 81.487%	pattern: 48	before: 528	now: 528
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
-coverage: 81.487%	pattern: 48	before: 528	now: 528
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
-coverage: 81.697%	pattern: 49	before: 528	now: 522
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
-coverage: 81.697%	pattern: 49	before: 522	now: 522
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:436
-coverage: 81.697%	pattern: 49	before: 522	now: 522
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
-coverage: 81.697%	pattern: 49	before: 522	now: 522
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
-coverage: 81.697%	pattern: 49	before: 522	now: 522
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
-coverage: 81.697%	pattern: 49	before: 522	now: 522
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
-coverage: 81.697%	pattern: 49	before: 522	now: 522
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
-coverage: 81.697%	pattern: 49	before: 522	now: 522
+[SOL] flip: 0, stem: 0, fault:280. flip_cnt: 0, stem_cnt: 696, fault_cnt:763
+coverage: 73.036%	pattern: 16	before: 787	now: 769
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
-coverage: 81.697%	pattern: 49	before: 522	now: 522
+coverage: 73.036%	pattern: 16	before: 769	now: 769
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
-coverage: 81.697%	pattern: 49	before: 522	now: 522
+[SOL] flip: 0, stem: 0, fault:21. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 73.107%	pattern: 17	before: 769	now: 767
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
-coverage: 81.697%	pattern: 49	before: 522	now: 522
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 73.457%	pattern: 18	before: 767	now: 757
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
-coverage: 81.697%	pattern: 49	before: 522	now: 522
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 73.457%	pattern: 18	before: 757	now: 757
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
-coverage: 81.942%	pattern: 50	before: 522	now: 515
+[SOL] flip: 0, stem: 0, fault:988. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 75.351%	pattern: 19	before: 757	now: 703
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
-coverage: 82.153%	pattern: 51	before: 515	now: 509
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 75.771%	pattern: 20	before: 703	now: 691
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
-coverage: 82.153%	pattern: 51	before: 509	now: 509
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 75.806%	pattern: 21	before: 691	now: 690
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
-coverage: 82.153%	pattern: 51	before: 509	now: 509
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 75.806%	pattern: 21	before: 690	now: 690
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
-coverage: 82.188%	pattern: 52	before: 509	now: 508
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 76.122%	pattern: 22	before: 690	now: 681
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
-coverage: 82.188%	pattern: 52	before: 508	now: 508
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 76.473%	pattern: 23	before: 681	now: 671
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
-coverage: 82.188%	pattern: 52	before: 508	now: 508
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 76.473%	pattern: 23	before: 671	now: 671
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
-coverage: 82.188%	pattern: 52	before: 508	now: 508
+[SOL] flip: 0, stem: 0, fault:52. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
+coverage: 76.613%	pattern: 24	before: 671	now: 667
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
-coverage: 82.188%	pattern: 52	before: 508	now: 508
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 76.823%	pattern: 25	before: 667	now: 661
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 696, fault_cnt:766
+coverage: 77.349%	pattern: 26	before: 661	now: 646
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 77.419%	pattern: 27	before: 646	now: 644
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 77.805%	pattern: 28	before: 644	now: 633
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 77.805%	pattern: 28	before: 633	now: 633
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 78.121%	pattern: 29	before: 633	now: 624
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 78.331%	pattern: 30	before: 624	now: 618
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 78.366%	pattern: 31	before: 618	now: 617
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 78.436%	pattern: 32	before: 617	now: 615
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 78.506%	pattern: 33	before: 615	now: 613
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 78.717%	pattern: 34	before: 613	now: 607
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 78.717%	pattern: 34	before: 607	now: 607
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 78.717%	pattern: 34	before: 607	now: 607
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 78.717%	pattern: 34	before: 607	now: 607
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 78.717%	pattern: 34	before: 607	now: 607
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 78.717%	pattern: 34	before: 607	now: 607
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 78.752%	pattern: 35	before: 607	now: 606
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 78.752%	pattern: 35	before: 606	now: 606
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 78.752%	pattern: 35	before: 606	now: 606
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:670
+coverage: 78.752%	pattern: 35	before: 606	now: 606
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 78.822%	pattern: 36	before: 606	now: 604
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 78.822%	pattern: 36	before: 604	now: 604
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 78.822%	pattern: 36	before: 604	now: 604
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 78.857%	pattern: 37	before: 604	now: 603
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 78.892%	pattern: 38	before: 603	now: 602
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 79.102%	pattern: 39	before: 602	now: 596
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 79.102%	pattern: 39	before: 596	now: 596
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 79.102%	pattern: 39	before: 596	now: 596
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 79.173%	pattern: 40	before: 596	now: 594
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 79.173%	pattern: 40	before: 594	now: 594
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 79.173%	pattern: 40	before: 594	now: 594
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 79.173%	pattern: 40	before: 594	now: 594
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 79.418%	pattern: 41	before: 594	now: 587
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 79.418%	pattern: 41	before: 587	now: 587
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 79.418%	pattern: 41	before: 587	now: 587
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 79.418%	pattern: 41	before: 587	now: 587
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 79.418%	pattern: 41	before: 587	now: 587
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:450
+coverage: 79.418%	pattern: 41	before: 587	now: 587
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 79.909%	pattern: 42	before: 587	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:423
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 79.909%	pattern: 42	before: 573	now: 573
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 79.979%	pattern: 43	before: 573	now: 571
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 79.979%	pattern: 43	before: 571	now: 571
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 79.979%	pattern: 43	before: 571	now: 571
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 79.979%	pattern: 43	before: 571	now: 571
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 79.979%	pattern: 43	before: 571	now: 571
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 79.979%	pattern: 43	before: 571	now: 571
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 80.119%	pattern: 44	before: 571	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 80.119%	pattern: 44	before: 567	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 80.119%	pattern: 44	before: 567	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 80.119%	pattern: 44	before: 567	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 80.119%	pattern: 44	before: 567	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 80.435%	pattern: 45	before: 567	now: 558
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 80.435%	pattern: 45	before: 558	now: 558
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
-coverage: 82.188%	pattern: 52	before: 508	now: 508
+coverage: 80.435%	pattern: 45	before: 558	now: 558
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
-coverage: 82.609%	pattern: 53	before: 508	now: 496
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 80.645%	pattern: 46	before: 558	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 80.645%	pattern: 46	before: 552	now: 552
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 80.715%	pattern: 47	before: 552	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:432
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 80.715%	pattern: 47	before: 550	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:551. flip_cnt: 0, stem_cnt: 696, fault_cnt:791
+coverage: 81.732%	pattern: 48	before: 550	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 81.732%	pattern: 48	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 81.732%	pattern: 48	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 81.732%	pattern: 48	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 81.732%	pattern: 48	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 81.872%	pattern: 49	before: 521	now: 517
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 81.872%	pattern: 49	before: 517	now: 517
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 81.872%	pattern: 49	before: 517	now: 517
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 81.872%	pattern: 49	before: 517	now: 517
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 81.872%	pattern: 49	before: 517	now: 517
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 81.872%	pattern: 49	before: 517	now: 517
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 81.872%	pattern: 49	before: 517	now: 517
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 81.872%	pattern: 49	before: 517	now: 517
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 82.468%	pattern: 50	before: 517	now: 500
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 82.468%	pattern: 50	before: 500	now: 500
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 82.609%	pattern: 51	before: 500	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:803
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:699
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 82.609%	pattern: 51	before: 496	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 82.924%	pattern: 52	before: 496	now: 487
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 82.924%	pattern: 52	before: 487	now: 487
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 82.924%	pattern: 52	before: 487	now: 487
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 82.924%	pattern: 52	before: 487	now: 487
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 696, fault_cnt:763
+coverage: 83.275%	pattern: 53	before: 487	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:465
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 83.275%	pattern: 53	before: 477	now: 477
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 83.590%	pattern: 54	before: 477	now: 468
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 83.590%	pattern: 54	before: 468	now: 468
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 83.590%	pattern: 54	before: 468	now: 468
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 83.871%	pattern: 55	before: 468	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:763
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:708
+coverage: 83.871%	pattern: 55	before: 460	now: 460
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:728
+coverage: 84.116%	pattern: 56	before: 460	now: 453
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 84.116%	pattern: 56	before: 453	now: 453
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 84.116%	pattern: 56	before: 453	now: 453
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 84.116%	pattern: 56	before: 453	now: 453
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 84.362%	pattern: 57	before: 453	now: 446
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:738
+coverage: 84.362%	pattern: 57	before: 446	now: 446
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 84.362%	pattern: 57	before: 446	now: 446
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 84.748%	pattern: 58	before: 446	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:461
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 84.748%	pattern: 58	before: 435	now: 435
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 84.783%	pattern: 59	before: 435	now: 434
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:777
+coverage: 84.818%	pattern: 60	before: 434	now: 433
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 84.818%	pattern: 60	before: 433	now: 433
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:427
+coverage: 84.818%	pattern: 60	before: 433	now: 433
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 84.818%	pattern: 60	before: 433	now: 433
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 84.818%	pattern: 60	before: 433	now: 433
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 85.133%	pattern: 61	before: 433	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:764
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:726
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:440
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 85.133%	pattern: 61	before: 424	now: 424
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 85.414%	pattern: 62	before: 424	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 85.414%	pattern: 62	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 85.414%	pattern: 62	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 85.414%	pattern: 62	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 85.414%	pattern: 62	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 85.414%	pattern: 62	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 85.624%	pattern: 63	before: 416	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 85.624%	pattern: 63	before: 410	now: 410
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:723
+coverage: 85.659%	pattern: 64	before: 410	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 85.659%	pattern: 64	before: 409	now: 409
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 86.010%	pattern: 65	before: 409	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:414
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:741
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:703
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:670
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 86.010%	pattern: 65	before: 399	now: 399
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:2775. flip_cnt: 0, stem_cnt: 696, fault_cnt:697
+coverage: 91.199%	pattern: 66	before: 399	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 91.199%	pattern: 66	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 91.199%	pattern: 66	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:455
+coverage: 91.199%	pattern: 66	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 91.199%	pattern: 66	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 91.199%	pattern: 66	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 91.199%	pattern: 66	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 91.199%	pattern: 66	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 91.199%	pattern: 66	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:723
+coverage: 91.269%	pattern: 67	before: 251	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:817
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:764
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:721
+coverage: 91.269%	pattern: 67	before: 249	now: 249
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 91.550%	pattern: 68	before: 249	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:465
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:752
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:778
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:441
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:447
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:767
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:697
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:784
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:807
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:722
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:426
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:736
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:697
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:683
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:763
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:729
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:476
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:761
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:731
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:466
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:374
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 91.550%	pattern: 68	before: 241	now: 241
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
-coverage: 82.609%	pattern: 53	before: 496	now: 496
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:466
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:758
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:737
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:429
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:792
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:761
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:441
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:783
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:465
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:783
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:758
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:745
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:786
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:732
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:775
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:756
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:765
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:450
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:810
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:734
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:440
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:480
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:433
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:832
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:702
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:476
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:480
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:692
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:743
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:438
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:753
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:761
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:443
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:402
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:455
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:450
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:436
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:449
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:731
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:804
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:698
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.550%	pattern: 68	before: 241	now: 241
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
+coverage: 91.760%	pattern: 69	before: 241	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:697
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:842
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:728
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:670
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:774
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:480
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:752
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:714
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:777
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:711
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:702
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:732
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:445
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:419
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:746
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:445
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:746
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:448
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:461
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:722
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:760
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:721
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:699
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:684
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:437
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:456
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:757
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:767
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:441
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:698
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:684
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:731
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:743
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:426
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:441
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:721
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:458
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:797
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:433
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:754
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:454
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:730
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:754
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:719
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:428
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:764
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:783
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:433
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:416
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:772
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:699
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:480
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:771
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:437
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:741
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:703
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:710
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:739
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:443
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:454
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:817
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:725
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:431
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:386
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:480
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:782
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:465
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:702
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:711
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:746
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:466
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:783
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:726
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:721
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:432
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:730
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:757
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:745
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:777
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:449
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:791
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:435
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:717
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:766
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:796
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:720
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:784
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:708
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:440
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:458
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:456
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:696
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:741
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:397
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:726
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:770
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:410
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:732
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:697
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:466
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:439
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 91.760%	pattern: 69	before: 235	now: 235
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 91.971%	pattern: 70	before: 235	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:440
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:434
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:456
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:670
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:780
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:765
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:427
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:450
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:767
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:703
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:409
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:787
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:726
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:784
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:747
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:794
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:432
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:729
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:721
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:741
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:711
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 91.971%	pattern: 70	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 92.216%	pattern: 71	before: 229	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:713
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:788
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:747
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:697
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:786
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:438
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:446
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:429
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:433
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:773
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:446
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:413
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:760
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:458
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:779
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:480
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:752
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:683
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:750
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:454
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:447
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:743
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:448
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:774
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:424
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:432
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:747
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:743
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:815
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:436
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:815
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:777
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:717
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:448
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:702
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:763
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:432
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:449
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:734
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:710
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:434
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:455
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:714
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 92.216%	pattern: 71	before: 222	now: 222
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 92.356%	pattern: 72	before: 222	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:723
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:722
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:772
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:794
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:739
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:725
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:739
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:753
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:457
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:777
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:455
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:747
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:775
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:710
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:742
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:736
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:433
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:440
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:724
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:465
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:466
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:771
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:779
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:783
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:731
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:448
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:731
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:730
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:757
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:724
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:713
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:718
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:450
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:729
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:803
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:703
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:739
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:449
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:724
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:699
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:455
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:786
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:778
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:726
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:731
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:456
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:726
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:732
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:743
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:439
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:745
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:785
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:752
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:436
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:457
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:728
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:723
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:757
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:423
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:783
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:730
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:430
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:793
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:435
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:683
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:815
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:777
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:762
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:788
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:434
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:799
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:461
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:747
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:757
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:779
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:684
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:777
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:742
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:447
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:717
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:746
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:790
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:731
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:436
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:430
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:756
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:750
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:683
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:699
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:753
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:791
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:425
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:720
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:416
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:741
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:732
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:756
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:455
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:777
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:809
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:719
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:767
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:437
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:696
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:433
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:456
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:696
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:701
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:776
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:718
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:742
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
+coverage: 92.356%	pattern: 72	before: 218	now: 218
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 92.637%	pattern: 73	before: 218	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:761
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:747
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:725
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:434
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:703
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:736
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:433
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 92.637%	pattern: 73	before: 210	now: 210
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:819
+coverage: 92.882%	pattern: 74	before: 210	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:773
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:724
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:702
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:736
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:699
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:670
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:710
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:403
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:746
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:480
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:722
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:781
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:696
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:457
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 92.882%	pattern: 74	before: 203	now: 203
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1083. flip_cnt: 0, stem_cnt: 696, fault_cnt:938
+coverage: 94.881%	pattern: 75	before: 203	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:722
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:749
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:794
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:423
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:791
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:466
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:421
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:465
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:831
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:385
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:426
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:458
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:476
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:717
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:812
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:718
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:447
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:732
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:457
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:625
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:728
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:770
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:708
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:725
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:779
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:455
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:761
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:461
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:684
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:698
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:692
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:750
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:423
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:450
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:723
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:730
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:712
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:767
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:722
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:480
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:747
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:411
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:707
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:708
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:730
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:783
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:536
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:708
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:729
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:724
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:725
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:458
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:674
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:796
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:458
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:401
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:457
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:455
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:466
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:454
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:456
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:697
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:726
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:670
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:648
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:764
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:769
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:692
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:742
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:423
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:752
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:543
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:433
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:714
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:699
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:751
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:445
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:710
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:500
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:422
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:768
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:732
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:425
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:571
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:463
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:756
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:660
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:447
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:439
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:454
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:561
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:772
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:724
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:439
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:721
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:795
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:454
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:684
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:458
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:432
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:767
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:692
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:461
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:638
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:430
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:686
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:456
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:697
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:425
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:751
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:808
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:728
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:457
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:670
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:748
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:695
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:745
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:792
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:711
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:443
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:726
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:724
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:477
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:431
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:431
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:751
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:550
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:748
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:782
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:514
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:527
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:708
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:628
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:775
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:772
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:467
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:585
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:475
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:661
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:637
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:679
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:517
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:685
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:603
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:457
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:579
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:582
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:469
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:465
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:705
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:542
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:636
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:635
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:738
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:751
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:450
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:722
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:677
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:684
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:622
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:676
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:472
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:675
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:717
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:738
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:415
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:797
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:449
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:642
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:703
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:822
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:640
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:732
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:567
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:752
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:788
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:558
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:719
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:743
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:540
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:599
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:692
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:597
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:476
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:750
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:485
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:415
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:690
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:720
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:684
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:578
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:576
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:713
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:541
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:502
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:503
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:766
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:733
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:710
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:385
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:752
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:611
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:454
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:757
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:744
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:586
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:445
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:512
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:552
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:776
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:544
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:484
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:564
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:747
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:471
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:461
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:421
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:427
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:672
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:457
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:669
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:423
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:700
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:692
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:445
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:651
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:520
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:623
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:508
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:618
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:526
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:739
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:704
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:740
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:448
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:746
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:537
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:654
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:545
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:416
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:452
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:498
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:682
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:734
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:612
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:522
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:547
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:602
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:459
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:831
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:634
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:721
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:797
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:691
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:474
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:663
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:722
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:549
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:752
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:616
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:575
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:533
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:528
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:495
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:460
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:562
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:487
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:727
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:402
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:451
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:662
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:647
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:548
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:649
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:587
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:580
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:456
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:525
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:627
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:671
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:604
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:658
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:446
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:595
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:489
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:709
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:478
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:639
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:696
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:493
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:666
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:389
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:617
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:714
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:755
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:473
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:724
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:688
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:656
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:506
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:615
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:653
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:524
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:593
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:621
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:589
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:650
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:555
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:799
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:591
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:613
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:632
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:657
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:532
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:626
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:570
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:496
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:750
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:716
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:572
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:756
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:447
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:466
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:438
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:753
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:510
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:551
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:605
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:606
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:481
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:719
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:668
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:577
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:694
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:504
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:511
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:488
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:491
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:652
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:696
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:631
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:565
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:692
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:644
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:462
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:581
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:600
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:461
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:483
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:774
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:557
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:687
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:518
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:633
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:546
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:556
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:492
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:560
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:464
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:607
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:529
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:680
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:521
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:619
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:515
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:610
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:620
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:538
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:608
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:513
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:507
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:535
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:659
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:569
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:673
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:486
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:601
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:563
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:664
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:566
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:584
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:505
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:519
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:706
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:645
+coverage: 94.881%	pattern: 75	before: 146	now: 146
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:614
+coverage: 94.881%	pattern: 75	before: 146	now: 146
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_c3540.bench.txt b/exp_result/ATPG-LS_c3540.bench.txt
index 8a35090..7a87ab6 100644
--- a/exp_result/ATPG-LS_c3540.bench.txt
+++ b/exp_result/ATPG-LS_c3540.bench.txt
@@ -8,693 +8,1305 @@ Gate:	1719
 Stem:	605
 Level:	14
 ================================ 
-[SOL] flip: 0, stem: 0, fault:11041. flip_cnt: 0, stem_cnt: 605, fault_cnt:582
-coverage: 16.928%	pattern: 1	before: 3438	now: 2856
+[SOL] flip: 0, stem: 0, fault:7212. flip_cnt: 0, stem_cnt: 605, fault_cnt:384
+coverage: 11.169%	pattern: 1	before: 3438	now: 3054
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:7292. flip_cnt: 0, stem_cnt: 605, fault_cnt:477
-coverage: 28.272%	pattern: 2	before: 2856	now: 2466
+[SOL] flip: 0, stem: 0, fault:6802. flip_cnt: 0, stem_cnt: 605, fault_cnt:474
+coverage: 21.582%	pattern: 2	before: 3054	now: 2696
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4577. flip_cnt: 0, stem_cnt: 605, fault_cnt:456
-coverage: 35.340%	pattern: 3	before: 2466	now: 2223
+[SOL] flip: 0, stem: 0, fault:4900. flip_cnt: 0, stem_cnt: 605, fault_cnt:409
+coverage: 29.145%	pattern: 3	before: 2696	now: 2436
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:3730. flip_cnt: 0, stem_cnt: 605, fault_cnt:535
-coverage: 41.245%	pattern: 4	before: 2223	now: 2020
+[SOL] flip: 0, stem: 0, fault:3097. flip_cnt: 0, stem_cnt: 605, fault_cnt:348
+coverage: 33.973%	pattern: 4	before: 2436	now: 2270
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2679. flip_cnt: 0, stem_cnt: 605, fault_cnt:453
-coverage: 45.346%	pattern: 5	before: 2020	now: 1879
+[SOL] flip: 0, stem: 0, fault:3420. flip_cnt: 0, stem_cnt: 605, fault_cnt:414
+coverage: 39.209%	pattern: 5	before: 2270	now: 2090
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5093. flip_cnt: 0, stem_cnt: 605, fault_cnt:658
-coverage: 53.170%	pattern: 6	before: 1879	now: 1610
+[SOL] flip: 0, stem: 0, fault:2812. flip_cnt: 0, stem_cnt: 605, fault_cnt:376
+coverage: 43.514%	pattern: 6	before: 2090	now: 1942
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 605, fault_cnt:305
-coverage: 54.741%	pattern: 7	before: 1610	now: 1556
+[SOL] flip: 0, stem: 0, fault:1577. flip_cnt: 0, stem_cnt: 605, fault_cnt:383
+coverage: 45.928%	pattern: 7	before: 1942	now: 1859
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 605, fault_cnt:273
-coverage: 55.381%	pattern: 8	before: 1556	now: 1534
+[SOL] flip: 0, stem: 0, fault:3230. flip_cnt: 0, stem_cnt: 605, fault_cnt:589
+coverage: 50.873%	pattern: 8	before: 1859	now: 1689
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1007. flip_cnt: 0, stem_cnt: 605, fault_cnt:396
-coverage: 56.923%	pattern: 9	before: 1534	now: 1481
+[SOL] flip: 0, stem: 0, fault:1178. flip_cnt: 0, stem_cnt: 605, fault_cnt:360
+coverage: 52.676%	pattern: 9	before: 1689	now: 1627
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1672. flip_cnt: 0, stem_cnt: 605, fault_cnt:464
-coverage: 59.482%	pattern: 10	before: 1481	now: 1393
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:163
+coverage: 52.967%	pattern: 10	before: 1627	now: 1617
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:328
-coverage: 59.948%	pattern: 11	before: 1393	now: 1377
+[SOL] flip: 0, stem: 0, fault:2052. flip_cnt: 0, stem_cnt: 605, fault_cnt:557
+coverage: 56.108%	pattern: 11	before: 1617	now: 1509
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 605, fault_cnt:364
-coverage: 61.547%	pattern: 12	before: 1377	now: 1322
+[SOL] flip: 0, stem: 0, fault:608. flip_cnt: 0, stem_cnt: 605, fault_cnt:462
+coverage: 57.039%	pattern: 12	before: 1509	now: 1477
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:931. flip_cnt: 0, stem_cnt: 605, fault_cnt:435
-coverage: 62.973%	pattern: 13	before: 1322	now: 1273
+[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 605, fault_cnt:496
+coverage: 58.639%	pattern: 13	before: 1477	now: 1422
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 605, fault_cnt:506
-coverage: 63.642%	pattern: 14	before: 1273	now: 1250
+[SOL] flip: 0, stem: 0, fault:1349. flip_cnt: 0, stem_cnt: 605, fault_cnt:569
+coverage: 60.704%	pattern: 14	before: 1422	now: 1351
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:304
-coverage: 64.107%	pattern: 15	before: 1250	now: 1234
+[SOL] flip: 0, stem: 0, fault:646. flip_cnt: 0, stem_cnt: 605, fault_cnt:336
+coverage: 61.693%	pattern: 15	before: 1351	now: 1317
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1843. flip_cnt: 0, stem_cnt: 605, fault_cnt:631
-coverage: 66.928%	pattern: 16	before: 1234	now: 1137
+[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 605, fault_cnt:571
+coverage: 63.060%	pattern: 16	before: 1317	now: 1270
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 605, fault_cnt:479
-coverage: 67.423%	pattern: 17	before: 1137	now: 1120
+[SOL] flip: 0, stem: 0, fault:646. flip_cnt: 0, stem_cnt: 605, fault_cnt:513
+coverage: 64.049%	pattern: 17	before: 1270	now: 1236
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:301
-coverage: 67.685%	pattern: 18	before: 1120	now: 1111
+[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 605, fault_cnt:452
+coverage: 64.543%	pattern: 18	before: 1236	now: 1219
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 605, fault_cnt:475
-coverage: 69.052%	pattern: 19	before: 1111	now: 1064
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
+coverage: 64.660%	pattern: 19	before: 1219	now: 1215
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:316
-coverage: 69.168%	pattern: 20	before: 1064	now: 1060
+[SOL] flip: 0, stem: 0, fault:722. flip_cnt: 0, stem_cnt: 605, fault_cnt:482
+coverage: 65.765%	pattern: 20	before: 1215	now: 1177
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:570. flip_cnt: 0, stem_cnt: 605, fault_cnt:424
-coverage: 70.041%	pattern: 21	before: 1060	now: 1030
+[SOL] flip: 0, stem: 0, fault:665. flip_cnt: 0, stem_cnt: 605, fault_cnt:421
+coverage: 66.783%	pattern: 21	before: 1177	now: 1142
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 605, fault_cnt:507
-coverage: 70.797%	pattern: 22	before: 1030	now: 1004
+[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 605, fault_cnt:479
+coverage: 67.539%	pattern: 22	before: 1142	now: 1116
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:684. flip_cnt: 0, stem_cnt: 605, fault_cnt:457
-coverage: 71.844%	pattern: 23	before: 1004	now: 968
+[SOL] flip: 0, stem: 0, fault:627. flip_cnt: 0, stem_cnt: 605, fault_cnt:438
+coverage: 68.499%	pattern: 23	before: 1116	now: 1083
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 605, fault_cnt:421
-coverage: 72.368%	pattern: 24	before: 968	now: 950
+[SOL] flip: 0, stem: 0, fault:608. flip_cnt: 0, stem_cnt: 605, fault_cnt:419
+coverage: 69.430%	pattern: 24	before: 1083	now: 1051
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1216. flip_cnt: 0, stem_cnt: 605, fault_cnt:488
-coverage: 74.229%	pattern: 25	before: 950	now: 886
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:515
+coverage: 69.663%	pattern: 25	before: 1051	now: 1043
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:684. flip_cnt: 0, stem_cnt: 605, fault_cnt:537
-coverage: 75.276%	pattern: 26	before: 886	now: 850
+[SOL] flip: 0, stem: 0, fault:1938. flip_cnt: 0, stem_cnt: 605, fault_cnt:636
+coverage: 72.629%	pattern: 26	before: 1043	now: 941
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:608. flip_cnt: 0, stem_cnt: 605, fault_cnt:571
-coverage: 76.207%	pattern: 27	before: 850	now: 818
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:294
+coverage: 72.717%	pattern: 27	before: 941	now: 938
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 605, fault_cnt:573
-coverage: 76.992%	pattern: 28	before: 818	now: 791
+[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:487
+coverage: 73.269%	pattern: 28	before: 938	now: 919
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 605, fault_cnt:642
-coverage: 77.487%	pattern: 29	before: 791	now: 774
+[SOL] flip: 0, stem: 0, fault:722. flip_cnt: 0, stem_cnt: 605, fault_cnt:607
+coverage: 74.375%	pattern: 29	before: 919	now: 881
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:632
-coverage: 77.778%	pattern: 30	before: 774	now: 764
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:504
+coverage: 74.520%	pattern: 30	before: 881	now: 876
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 605, fault_cnt:401
-coverage: 78.418%	pattern: 31	before: 764	now: 742
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:506
+coverage: 74.724%	pattern: 31	before: 876	now: 869
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:445
-coverage: 78.505%	pattern: 32	before: 742	now: 739
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 605, fault_cnt:383
+coverage: 74.898%	pattern: 32	before: 869	now: 863
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:567
-coverage: 78.592%	pattern: 33	before: 739	now: 736
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:558
+coverage: 74.927%	pattern: 33	before: 863	now: 862
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:216
-coverage: 78.738%	pattern: 34	before: 736	now: 731
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:513
-coverage: 78.738%	pattern: 34	before: 731	now: 731
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:572
-coverage: 78.738%	pattern: 34	before: 731	now: 731
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:366
-coverage: 78.738%	pattern: 34	before: 731	now: 731
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 605, fault_cnt:480
-coverage: 79.145%	pattern: 35	before: 731	now: 717
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
-coverage: 79.727%	pattern: 36	before: 717	now: 697
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:458
-coverage: 80.076%	pattern: 37	before: 697	now: 685
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:341
-coverage: 80.163%	pattern: 38	before: 685	now: 682
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 605, fault_cnt:506
-coverage: 80.337%	pattern: 39	before: 682	now: 676
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:523
-coverage: 80.890%	pattern: 40	before: 676	now: 657
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:479
-coverage: 81.443%	pattern: 41	before: 657	now: 638
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:469
-coverage: 81.472%	pattern: 42	before: 638	now: 637
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:643
-coverage: 81.617%	pattern: 43	before: 637	now: 632
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:557
-coverage: 81.617%	pattern: 43	before: 632	now: 632
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:455
-coverage: 81.763%	pattern: 44	before: 632	now: 627
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:517
-coverage: 81.850%	pattern: 45	before: 627	now: 624
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:520
-coverage: 82.083%	pattern: 46	before: 624	now: 616
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:396
-coverage: 82.083%	pattern: 46	before: 616	now: 616
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:539
-coverage: 82.112%	pattern: 47	before: 616	now: 615
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:344
-coverage: 82.315%	pattern: 48	before: 615	now: 608
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:478
-coverage: 82.461%	pattern: 49	before: 608	now: 603
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:613
-coverage: 82.752%	pattern: 50	before: 603	now: 593
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:468
-coverage: 82.752%	pattern: 50	before: 593	now: 593
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:454
-coverage: 82.839%	pattern: 51	before: 593	now: 590
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:328
-coverage: 82.839%	pattern: 51	before: 590	now: 590
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
-coverage: 82.839%	pattern: 51	before: 590	now: 590
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:402
-coverage: 82.868%	pattern: 52	before: 590	now: 589
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:369
-coverage: 82.868%	pattern: 52	before: 589	now: 589
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:434
-coverage: 82.868%	pattern: 52	before: 589	now: 589
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:539
-coverage: 82.926%	pattern: 53	before: 589	now: 587
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:489
-coverage: 82.926%	pattern: 53	before: 587	now: 587
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:465
-coverage: 82.926%	pattern: 53	before: 587	now: 587
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:367
-coverage: 82.955%	pattern: 54	before: 587	now: 586
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:371
-coverage: 83.072%	pattern: 55	before: 586	now: 582
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:616
-coverage: 83.537%	pattern: 56	before: 582	now: 566
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:366
-coverage: 83.566%	pattern: 57	before: 566	now: 565
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:241
-coverage: 83.566%	pattern: 57	before: 565	now: 565
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:454
-coverage: 83.595%	pattern: 58	before: 565	now: 564
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:394
-coverage: 83.595%	pattern: 58	before: 564	now: 564
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:469
-coverage: 83.595%	pattern: 58	before: 564	now: 564
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 605, fault_cnt:442
-coverage: 84.002%	pattern: 59	before: 564	now: 550
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:510
-coverage: 84.002%	pattern: 59	before: 550	now: 550
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:447
-coverage: 84.002%	pattern: 59	before: 550	now: 550
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:503
-coverage: 84.264%	pattern: 60	before: 550	now: 541
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:191
-coverage: 84.264%	pattern: 60	before: 541	now: 541
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:337
-coverage: 84.264%	pattern: 60	before: 541	now: 541
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 605, fault_cnt:413
-coverage: 85.079%	pattern: 61	before: 541	now: 513
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:569
-coverage: 85.195%	pattern: 62	before: 513	now: 509
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:529
-coverage: 85.224%	pattern: 63	before: 509	now: 508
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:293
-coverage: 85.224%	pattern: 63	before: 508	now: 508
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:306
-coverage: 85.224%	pattern: 63	before: 508	now: 508
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:516
-coverage: 85.282%	pattern: 64	before: 508	now: 506
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:290
-coverage: 85.311%	pattern: 65	before: 506	now: 505
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
-coverage: 85.311%	pattern: 65	before: 505	now: 505
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:532
-coverage: 85.311%	pattern: 65	before: 505	now: 505
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:309
-coverage: 85.311%	pattern: 65	before: 505	now: 505
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:480
-coverage: 85.311%	pattern: 65	before: 505	now: 505
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:333
-coverage: 85.340%	pattern: 66	before: 505	now: 504
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:507
-coverage: 85.573%	pattern: 67	before: 504	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
-coverage: 85.573%	pattern: 67	before: 496	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:429
-coverage: 85.573%	pattern: 67	before: 496	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:483
-coverage: 85.573%	pattern: 67	before: 496	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:551
-coverage: 85.718%	pattern: 68	before: 496	now: 491
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:425
-coverage: 85.748%	pattern: 69	before: 491	now: 490
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:285
-coverage: 85.748%	pattern: 69	before: 490	now: 490
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:385
-coverage: 86.009%	pattern: 70	before: 490	now: 481
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:415
-coverage: 86.009%	pattern: 70	before: 481	now: 481
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:288
-coverage: 86.009%	pattern: 70	before: 481	now: 481
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:490
-coverage: 86.097%	pattern: 71	before: 481	now: 478
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 605, fault_cnt:396
-coverage: 86.678%	pattern: 72	before: 478	now: 458
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:467
-coverage: 86.678%	pattern: 72	before: 458	now: 458
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
-coverage: 86.969%	pattern: 73	before: 458	now: 448
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:387
-coverage: 86.969%	pattern: 73	before: 448	now: 448
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:127
-coverage: 86.969%	pattern: 73	before: 448	now: 448
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:453
-coverage: 86.998%	pattern: 74	before: 448	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:591
-coverage: 86.998%	pattern: 74	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:481
-coverage: 86.998%	pattern: 74	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:544
-coverage: 86.998%	pattern: 74	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:450
-coverage: 86.998%	pattern: 74	before: 447	now: 447
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:307
-coverage: 87.260%	pattern: 75	before: 447	now: 438
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:508
-coverage: 87.289%	pattern: 76	before: 438	now: 437
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:572
-coverage: 87.289%	pattern: 76	before: 437	now: 437
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:404
-coverage: 87.289%	pattern: 76	before: 437	now: 437
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:565
-coverage: 87.289%	pattern: 76	before: 437	now: 437
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:387
-coverage: 87.405%	pattern: 77	before: 437	now: 433
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:604
-coverage: 87.405%	pattern: 77	before: 433	now: 433
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:567
-coverage: 87.405%	pattern: 77	before: 433	now: 433
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:602
-coverage: 87.522%	pattern: 78	before: 433	now: 429
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522
-coverage: 87.522%	pattern: 78	before: 429	now: 429
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:400
-coverage: 87.522%	pattern: 78	before: 429	now: 429
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:537
-coverage: 87.522%	pattern: 78	before: 429	now: 429
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:551
-coverage: 87.522%	pattern: 78	before: 429	now: 429
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:383
-coverage: 87.580%	pattern: 79	before: 429	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:473
-coverage: 87.580%	pattern: 79	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:336
-coverage: 87.580%	pattern: 79	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:512
-coverage: 87.580%	pattern: 79	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:432
-coverage: 87.580%	pattern: 79	before: 427	now: 427
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
-coverage: 87.580%	pattern: 79	before: 427	now: 427
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:382
+coverage: 74.927%	pattern: 33	before: 862	now: 862
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:475
-coverage: 87.580%	pattern: 79	before: 427	now: 427
+coverage: 74.927%	pattern: 33	before: 862	now: 862
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:257
-coverage: 87.580%	pattern: 79	before: 427	now: 427
+[SOL] flip: 0, stem: 0, fault:1302. flip_cnt: 0, stem_cnt: 605, fault_cnt:472
+coverage: 76.934%	pattern: 34	before: 862	now: 793
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:239
-coverage: 87.580%	pattern: 79	before: 427	now: 427
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:429
+coverage: 76.934%	pattern: 34	before: 793	now: 793
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:526
-coverage: 87.580%	pattern: 79	before: 427	now: 427
+[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 605, fault_cnt:445
+coverage: 77.574%	pattern: 35	before: 793	now: 771
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377
-coverage: 87.580%	pattern: 79	before: 427	now: 427
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:441
+coverage: 77.923%	pattern: 36	before: 771	now: 759
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495
-coverage: 87.580%	pattern: 79	before: 427	now: 427
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:212
+coverage: 77.952%	pattern: 37	before: 759	now: 758
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:520
-coverage: 87.638%	pattern: 80	before: 427	now: 425
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:531
+coverage: 78.418%	pattern: 38	before: 758	now: 742
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:529
-coverage: 87.842%	pattern: 81	before: 425	now: 418
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:482
+coverage: 78.883%	pattern: 39	before: 742	now: 726
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:318
-coverage: 87.842%	pattern: 81	before: 418	now: 418
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:370
-coverage: 87.842%	pattern: 81	before: 418	now: 418
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:334
-coverage: 87.842%	pattern: 81	before: 418	now: 418
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484
-coverage: 87.842%	pattern: 81	before: 418	now: 418
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:228
-coverage: 87.842%	pattern: 81	before: 418	now: 418
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:510
-coverage: 87.842%	pattern: 81	before: 418	now: 418
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:292
-coverage: 87.842%	pattern: 81	before: 418	now: 418
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:586
-coverage: 88.191%	pattern: 82	before: 418	now: 406
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:341
-coverage: 88.191%	pattern: 82	before: 406	now: 406
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:315
-coverage: 88.191%	pattern: 82	before: 406	now: 406
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
-coverage: 88.191%	pattern: 82	before: 406	now: 406
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:393
-coverage: 88.336%	pattern: 83	before: 406	now: 401
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:483
-coverage: 88.336%	pattern: 83	before: 401	now: 401
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:602
-coverage: 88.598%	pattern: 84	before: 401	now: 392
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:308
-coverage: 88.598%	pattern: 84	before: 392	now: 392
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:552
-coverage: 88.598%	pattern: 84	before: 392	now: 392
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:427
-coverage: 88.598%	pattern: 84	before: 392	now: 392
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:392
-coverage: 88.627%	pattern: 85	before: 392	now: 391
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:436
-coverage: 88.627%	pattern: 85	before: 391	now: 391
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:576
-coverage: 88.627%	pattern: 85	before: 391	now: 391
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:540
+coverage: 78.999%	pattern: 40	before: 726	now: 722
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:523
-coverage: 88.627%	pattern: 85	before: 391	now: 391
+coverage: 78.999%	pattern: 40	before: 722	now: 722
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:518
-coverage: 88.627%	pattern: 85	before: 391	now: 391
+[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 605, fault_cnt:463
+coverage: 79.407%	pattern: 41	before: 722	now: 708
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:558
-coverage: 88.627%	pattern: 85	before: 391	now: 391
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:459
-coverage: 88.656%	pattern: 86	before: 391	now: 390
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:401
-coverage: 88.656%	pattern: 86	before: 390	now: 390
+[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:474
+coverage: 79.959%	pattern: 42	before: 708	now: 689
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:488
-coverage: 88.656%	pattern: 86	before: 390	now: 390
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:369
-coverage: 88.656%	pattern: 86	before: 390	now: 390
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:253
-coverage: 88.656%	pattern: 86	before: 390	now: 390
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:530
-coverage: 88.656%	pattern: 86	before: 390	now: 390
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:559
-coverage: 88.656%	pattern: 86	before: 390	now: 390
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
-coverage: 88.656%	pattern: 86	before: 390	now: 390
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:236
-coverage: 88.656%	pattern: 86	before: 390	now: 390
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:634
-coverage: 88.714%	pattern: 87	before: 390	now: 388
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:478
-coverage: 88.714%	pattern: 87	before: 388	now: 388
+coverage: 79.959%	pattern: 42	before: 689	now: 689
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:269
-coverage: 88.714%	pattern: 87	before: 388	now: 388
+coverage: 79.959%	pattern: 42	before: 689	now: 689
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:519
-coverage: 89.005%	pattern: 88	before: 388	now: 378
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:582
+coverage: 80.076%	pattern: 43	before: 689	now: 685
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484
-coverage: 89.005%	pattern: 88	before: 378	now: 378
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:329
+coverage: 80.279%	pattern: 44	before: 685	now: 678
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461
-coverage: 89.005%	pattern: 88	before: 378	now: 378
+[SOL] flip: 0, stem: 0, fault:627. flip_cnt: 0, stem_cnt: 605, fault_cnt:606
+coverage: 81.239%	pattern: 45	before: 678	now: 645
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:447
-coverage: 89.005%	pattern: 88	before: 378	now: 378
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 605, fault_cnt:390
+coverage: 81.559%	pattern: 46	before: 645	now: 634
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461
-coverage: 89.005%	pattern: 88	before: 378	now: 378
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:403
+coverage: 81.646%	pattern: 47	before: 634	now: 631
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:504
-coverage: 89.005%	pattern: 88	before: 378	now: 378
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:470
+coverage: 81.646%	pattern: 47	before: 631	now: 631
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:488
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:314
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:460
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:285
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:473
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:626
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:600
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:520
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:595
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:464
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:460
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:272
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:459
-coverage: 89.005%	pattern: 88	before: 378	now: 378
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 605, fault_cnt:416
-coverage: 89.529%	pattern: 89	before: 378	now: 360
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:578
-coverage: 89.587%	pattern: 90	before: 360	now: 358
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
-coverage: 89.616%	pattern: 91	before: 358	now: 357
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:443
-coverage: 89.616%	pattern: 91	before: 357	now: 357
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377
-coverage: 89.616%	pattern: 91	before: 357	now: 357
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:342
-coverage: 89.732%	pattern: 92	before: 357	now: 353
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:249
-coverage: 89.732%	pattern: 92	before: 353	now: 353
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:343
-coverage: 89.732%	pattern: 92	before: 353	now: 353
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:508
-coverage: 89.732%	pattern: 92	before: 353	now: 353
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:486
-coverage: 89.791%	pattern: 93	before: 353	now: 351
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:477
-coverage: 89.791%	pattern: 93	before: 351	now: 351
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:359
-coverage: 89.791%	pattern: 93	before: 351	now: 351
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:279
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:539
+coverage: 82.112%	pattern: 48	before: 631	now: 615
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:502
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+coverage: 82.112%	pattern: 48	before: 615	now: 615
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:539
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 605, fault_cnt:489
+coverage: 82.490%	pattern: 49	before: 615	now: 602
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:562
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:463
+coverage: 82.839%	pattern: 50	before: 602	now: 590
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:452
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:381
+coverage: 82.868%	pattern: 51	before: 590	now: 589
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:516
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:497
+coverage: 82.868%	pattern: 51	before: 589	now: 589
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:463
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:536
+coverage: 82.868%	pattern: 51	before: 589	now: 589
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:477
+coverage: 82.868%	pattern: 51	before: 589	now: 589
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:532
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:505
+coverage: 82.868%	pattern: 51	before: 589	now: 589
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:269
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:410
+coverage: 83.159%	pattern: 52	before: 589	now: 579
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 605, fault_cnt:573
+coverage: 83.741%	pattern: 53	before: 579	now: 559
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495
+coverage: 83.741%	pattern: 53	before: 559	now: 559
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:620
+coverage: 83.857%	pattern: 54	before: 559	now: 555
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:393
+coverage: 83.857%	pattern: 54	before: 555	now: 555
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:441
+coverage: 83.915%	pattern: 55	before: 555	now: 553
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:573
+coverage: 84.148%	pattern: 56	before: 553	now: 545
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:261
+coverage: 84.177%	pattern: 57	before: 545	now: 544
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:527
+coverage: 84.729%	pattern: 58	before: 544	now: 525
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:300
+coverage: 84.759%	pattern: 59	before: 525	now: 524
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:566
+coverage: 84.759%	pattern: 59	before: 524	now: 524
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:571
+coverage: 84.759%	pattern: 59	before: 524	now: 524
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:357
+coverage: 84.846%	pattern: 60	before: 524	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:511
+coverage: 84.846%	pattern: 60	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:506
+coverage: 84.846%	pattern: 60	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:588
+coverage: 84.846%	pattern: 60	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:528
+coverage: 84.846%	pattern: 60	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:567
+coverage: 84.846%	pattern: 60	before: 521	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:454
+coverage: 84.875%	pattern: 61	before: 521	now: 520
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:474
+coverage: 84.991%	pattern: 62	before: 520	now: 516
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:530
+coverage: 85.020%	pattern: 63	before: 516	now: 515
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:512
+coverage: 85.020%	pattern: 63	before: 515	now: 515
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:393
+coverage: 85.020%	pattern: 63	before: 515	now: 515
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:496
+coverage: 85.311%	pattern: 64	before: 515	now: 505
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:596
+coverage: 85.340%	pattern: 65	before: 505	now: 504
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:518
+coverage: 85.340%	pattern: 65	before: 504	now: 504
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:461
+coverage: 85.369%	pattern: 66	before: 504	now: 503
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:468
+coverage: 85.515%	pattern: 67	before: 503	now: 498
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:431
+coverage: 85.573%	pattern: 68	before: 498	now: 496
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:440
+coverage: 85.777%	pattern: 69	before: 496	now: 489
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:655
+coverage: 85.864%	pattern: 70	before: 489	now: 486
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:468
+coverage: 85.864%	pattern: 70	before: 486	now: 486
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 605, fault_cnt:487
+coverage: 86.446%	pattern: 71	before: 486	now: 466
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:341
+coverage: 86.446%	pattern: 71	before: 466	now: 466
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:420
+coverage: 86.998%	pattern: 72	before: 466	now: 447
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:510
+coverage: 87.056%	pattern: 73	before: 447	now: 445
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:509
+coverage: 87.056%	pattern: 73	before: 445	now: 445
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:442
+coverage: 87.086%	pattern: 74	before: 445	now: 444
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:339
+coverage: 87.086%	pattern: 74	before: 444	now: 444
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:468
+coverage: 87.086%	pattern: 74	before: 444	now: 444
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:261
+coverage: 87.086%	pattern: 74	before: 444	now: 444
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:492
+coverage: 87.086%	pattern: 74	before: 444	now: 444
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+coverage: 87.086%	pattern: 74	before: 444	now: 444
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:474
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:530
+coverage: 87.086%	pattern: 74	before: 444	now: 444
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:360
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:516
+coverage: 87.086%	pattern: 74	before: 444	now: 444
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:283
-coverage: 89.791%	pattern: 93	before: 351	now: 351
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:533
+coverage: 87.202%	pattern: 75	before: 444	now: 440
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:313
-coverage: 89.820%	pattern: 94	before: 351	now: 350
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:607
+coverage: 87.260%	pattern: 76	before: 440	now: 438
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:391
+coverage: 87.318%	pattern: 77	before: 438	now: 436
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:418
+coverage: 87.376%	pattern: 78	before: 436	now: 434
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:494
+coverage: 87.376%	pattern: 78	before: 434	now: 434
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:357
+coverage: 87.405%	pattern: 79	before: 434	now: 433
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:424
+coverage: 87.435%	pattern: 80	before: 433	now: 432
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:546
+coverage: 87.435%	pattern: 80	before: 432	now: 432
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:371
+coverage: 87.464%	pattern: 81	before: 432	now: 431
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:311
+coverage: 87.464%	pattern: 81	before: 431	now: 431
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:426
+coverage: 87.493%	pattern: 82	before: 431	now: 430
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:435
+coverage: 87.551%	pattern: 83	before: 430	now: 428
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:525
+coverage: 87.551%	pattern: 83	before: 428	now: 428
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:401
+coverage: 87.696%	pattern: 84	before: 428	now: 423
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:547
+coverage: 87.696%	pattern: 84	before: 423	now: 423
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:358
+coverage: 87.725%	pattern: 85	before: 423	now: 422
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:403
+coverage: 87.725%	pattern: 85	before: 422	now: 422
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:512
+coverage: 87.725%	pattern: 85	before: 422	now: 422
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:412
+coverage: 87.725%	pattern: 85	before: 422	now: 422
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:381
+coverage: 87.842%	pattern: 86	before: 422	now: 418
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:435
+coverage: 87.900%	pattern: 87	before: 418	now: 416
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:507
-coverage: 89.820%	pattern: 94	before: 350	now: 350
+coverage: 87.900%	pattern: 87	before: 416	now: 416
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:430
-coverage: 90.081%	pattern: 95	before: 350	now: 341
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:540
+coverage: 87.900%	pattern: 87	before: 416	now: 416
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:374
-coverage: 90.081%	pattern: 95	before: 341	now: 341
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:557
+coverage: 87.900%	pattern: 87	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:208
+coverage: 87.900%	pattern: 87	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:460
+coverage: 87.958%	pattern: 88	before: 416	now: 414
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:534
+coverage: 87.958%	pattern: 88	before: 414	now: 414
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:331
+coverage: 87.958%	pattern: 88	before: 414	now: 414
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:610
+coverage: 88.220%	pattern: 89	before: 414	now: 405
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:395
+coverage: 88.220%	pattern: 89	before: 405	now: 405
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:490
+coverage: 88.220%	pattern: 89	before: 405	now: 405
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:466
+coverage: 88.220%	pattern: 89	before: 405	now: 405
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:525
+coverage: 88.220%	pattern: 89	before: 405	now: 405
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:411
+coverage: 88.220%	pattern: 89	before: 405	now: 405
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:488
+coverage: 88.278%	pattern: 90	before: 405	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:508
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:369
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:508
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:474
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:401
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:464
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:541
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:514
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:380
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:401
+coverage: 88.278%	pattern: 90	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:411
+coverage: 88.307%	pattern: 91	before: 403	now: 402
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:407
+coverage: 88.307%	pattern: 91	before: 402	now: 402
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:408
+coverage: 88.365%	pattern: 92	before: 402	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:531
+coverage: 88.365%	pattern: 92	before: 400	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:561
+coverage: 88.424%	pattern: 93	before: 400	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:389
+coverage: 88.540%	pattern: 94	before: 398	now: 394
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:433
+coverage: 88.540%	pattern: 94	before: 394	now: 394
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:424
+coverage: 88.685%	pattern: 95	before: 394	now: 389
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:504
+coverage: 88.685%	pattern: 95	before: 389	now: 389
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:372
+coverage: 88.685%	pattern: 95	before: 389	now: 389
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:506
+coverage: 88.685%	pattern: 95	before: 389	now: 389
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:574
+coverage: 88.685%	pattern: 95	before: 389	now: 389
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:460
+coverage: 88.685%	pattern: 95	before: 389	now: 389
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:349
+coverage: 88.685%	pattern: 95	before: 389	now: 389
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:277
+coverage: 88.685%	pattern: 95	before: 389	now: 389
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:377
+coverage: 88.976%	pattern: 96	before: 389	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:491
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:531
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:327
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:512
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:442
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:402
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:488
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:349
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:507
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:220
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:330
+coverage: 88.976%	pattern: 96	before: 379	now: 379
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:487
-coverage: 90.081%	pattern: 95	before: 341	now: 341
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:442
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:565
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:376
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:568
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:426
+coverage: 88.976%	pattern: 96	before: 379	now: 379
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:465
+coverage: 89.005%	pattern: 97	before: 379	now: 378
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522
-coverage: 90.081%	pattern: 95	before: 341	now: 341
+coverage: 89.005%	pattern: 97	before: 378	now: 378
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:395
-coverage: 90.169%	pattern: 96	before: 341	now: 338
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:543
+coverage: 89.005%	pattern: 97	before: 378	now: 378
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377
-coverage: 90.169%	pattern: 96	before: 338	now: 338
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:403
+coverage: 89.092%	pattern: 98	before: 378	now: 375
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:293
-coverage: 90.169%	pattern: 96	before: 338	now: 338
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:284
+coverage: 89.092%	pattern: 98	before: 375	now: 375
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:545
-coverage: 90.169%	pattern: 96	before: 338	now: 338
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:427
+coverage: 89.092%	pattern: 98	before: 375	now: 375
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:440
+coverage: 89.151%	pattern: 99	before: 375	now: 373
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:481
+coverage: 89.151%	pattern: 99	before: 373	now: 373
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:632
+coverage: 89.500%	pattern: 100	before: 373	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:353
+coverage: 89.529%	pattern: 101	before: 361	now: 360
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:470
+coverage: 89.529%	pattern: 101	before: 360	now: 360
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:358
+coverage: 89.529%	pattern: 101	before: 360	now: 360
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
+coverage: 89.529%	pattern: 101	before: 360	now: 360
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:516
+coverage: 89.645%	pattern: 102	before: 360	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:508
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:445
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:406
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:301
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:435
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:555
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:444
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:283
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:335
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:503
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:568
+coverage: 89.645%	pattern: 102	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:503
+coverage: 89.703%	pattern: 103	before: 356	now: 354
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
+coverage: 89.703%	pattern: 103	before: 354	now: 354
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522
+coverage: 89.703%	pattern: 103	before: 354	now: 354
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:480
+coverage: 89.703%	pattern: 103	before: 354	now: 354
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:387
+coverage: 89.820%	pattern: 104	before: 354	now: 350
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:496
+coverage: 89.820%	pattern: 104	before: 350	now: 350
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461
+coverage: 89.820%	pattern: 104	before: 350	now: 350
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:577
+coverage: 89.849%	pattern: 105	before: 350	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:270
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:479
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:494
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:544
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:521
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:369
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:634
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:480
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:444
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:463
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:541
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:573
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:504
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:560
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:493
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:370
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:393
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:396
+coverage: 89.849%	pattern: 105	before: 349	now: 349
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:439
+coverage: 89.965%	pattern: 106	before: 349	now: 345
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:515
+coverage: 89.965%	pattern: 106	before: 345	now: 345
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:471
+coverage: 89.965%	pattern: 106	before: 345	now: 345
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:496
+coverage: 90.081%	pattern: 107	before: 345	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:381
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:528
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:283
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:537
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:625
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:581
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:456
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:504
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:486
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:523
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:457
+coverage: 90.081%	pattern: 107	before: 341	now: 341
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:420
+coverage: 90.343%	pattern: 108	before: 341	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:458
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:418
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:395
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:470
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:436
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:453
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:480
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:432
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:330
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:477
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:441
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:493
+coverage: 90.343%	pattern: 108	before: 332	now: 332
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:386
+coverage: 90.634%	pattern: 109	before: 332	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 605, fault_cnt:490
+coverage: 91.012%	pattern: 110	before: 322	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:510
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:542
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:464
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:556
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:468
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:516
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:276
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:294
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:441
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:559
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:365
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:438
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:407
+coverage: 91.012%	pattern: 110	before: 309	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:417
+coverage: 91.245%	pattern: 111	before: 309	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:389
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:483
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:383
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:533
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:466
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:255
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:525
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:363
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:519
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:323
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:325
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:445
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:441
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:504
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:542
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:333
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:284
+coverage: 91.245%	pattern: 111	before: 301	now: 301
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:313
+coverage: 91.274%	pattern: 112	before: 301	now: 300
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:533
+coverage: 91.274%	pattern: 112	before: 300	now: 300
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:456
+coverage: 91.332%	pattern: 113	before: 300	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:330
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:481
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:600
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:534
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:486
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:266
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:398
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:565
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:446
+coverage: 91.332%	pattern: 113	before: 298	now: 298
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:448
+coverage: 91.449%	pattern: 114	before: 298	now: 294
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:521
+coverage: 91.449%	pattern: 114	before: 294	now: 294
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:372
+coverage: 91.536%	pattern: 115	before: 294	now: 291
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:467
+coverage: 91.536%	pattern: 115	before: 291	now: 291
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:511
+coverage: 91.536%	pattern: 115	before: 291	now: 291
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:561
+coverage: 91.536%	pattern: 115	before: 291	now: 291
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:327
+coverage: 91.536%	pattern: 115	before: 291	now: 291
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 605, fault_cnt:260
+coverage: 91.914%	pattern: 116	before: 291	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:551
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:333
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:497
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:481
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:390
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:432
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:568
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:482
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:470
+coverage: 91.914%	pattern: 116	before: 278	now: 278
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
+coverage: 91.972%	pattern: 117	before: 278	now: 276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:475
+coverage: 91.972%	pattern: 117	before: 276	now: 276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:541
+coverage: 91.972%	pattern: 117	before: 276	now: 276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:569
+coverage: 91.972%	pattern: 117	before: 276	now: 276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:493
+coverage: 91.972%	pattern: 117	before: 276	now: 276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:490
+coverage: 91.972%	pattern: 117	before: 276	now: 276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:605
+coverage: 91.972%	pattern: 117	before: 276	now: 276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:493
+coverage: 91.972%	pattern: 117	before: 276	now: 276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:451
+coverage: 92.118%	pattern: 118	before: 276	now: 271
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:482
+coverage: 92.147%	pattern: 119	before: 271	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:415
+coverage: 92.147%	pattern: 119	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:575
+coverage: 92.147%	pattern: 119	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:526
+coverage: 92.147%	pattern: 119	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:241
+coverage: 92.147%	pattern: 119	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:365
+coverage: 92.147%	pattern: 119	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:509
+coverage: 92.147%	pattern: 119	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461
+coverage: 92.147%	pattern: 119	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:521
+coverage: 92.147%	pattern: 119	before: 270	now: 270
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:391
+coverage: 92.292%	pattern: 120	before: 270	now: 265
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:538
+coverage: 92.350%	pattern: 121	before: 265	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:452
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:530
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:559
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:534
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:306
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:246
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:152
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:550
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:506
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:501
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:512
+coverage: 92.350%	pattern: 121	before: 263	now: 263
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:390
+coverage: 92.467%	pattern: 122	before: 263	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:490
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:500
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:466
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:476
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:465
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:498
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:399
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:514
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:457
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:556
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:590
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:348
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:519
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:440
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:485
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:324
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:505
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:525
+coverage: 92.467%	pattern: 122	before: 259	now: 259
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:469
+coverage: 92.583%	pattern: 123	before: 259	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:517
+coverage: 92.583%	pattern: 123	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:540
+coverage: 92.583%	pattern: 123	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:295
+coverage: 92.583%	pattern: 123	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:312
+coverage: 92.583%	pattern: 123	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:518
+coverage: 92.583%	pattern: 123	before: 255	now: 255
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:445
+coverage: 92.641%	pattern: 124	before: 255	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:507
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:402
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:511
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:491
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:406
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:448
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:338
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:540
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:526
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:359
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:524
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:455
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:295
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:601
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:529
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:329
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:423
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:455
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:480
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:359
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:493
+coverage: 92.641%	pattern: 124	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 605, fault_cnt:516
+coverage: 92.816%	pattern: 125	before: 253	now: 247
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:496
+coverage: 92.816%	pattern: 125	before: 247	now: 247
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:509
+coverage: 92.816%	pattern: 125	before: 247	now: 247
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:465
+coverage: 92.816%	pattern: 125	before: 247	now: 247
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522
+coverage: 92.816%	pattern: 125	before: 247	now: 247
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:491
+coverage: 92.816%	pattern: 125	before: 247	now: 247
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:432
+coverage: 92.932%	pattern: 126	before: 247	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:530
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:541
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:526
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:577
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:389
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:453
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:454
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:512
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:344
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:313
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:448
+coverage: 92.932%	pattern: 126	before: 243	now: 243
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:565
+coverage: 92.932%	pattern: 126	before: 243	now: 243
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_c432.bench.txt b/exp_result/ATPG-LS_c432.bench.txt
index 1078c90..237ee9a 100644
--- a/exp_result/ATPG-LS_c432.bench.txt
+++ b/exp_result/ATPG-LS_c432.bench.txt
@@ -8,88104 +8,180156 @@ Gate:	196
 Stem:	96
 Level:	6
 ================================ 
-[SOL] flip: 0, stem: 0, fault:422. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 12.245%	pattern: 1	before: 392	now: 344
+[SOL] flip: 0, stem: 0, fault:460. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 11.735%	pattern: 1	before: 392	now: 346
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:158. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 24.235%	pattern: 2	before: 344	now: 297
+[SOL] flip: 0, stem: 0, fault:967. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 36.480%	pattern: 2	before: 346	now: 249
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:753. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 34.439%	pattern: 3	before: 297	now: 257
+[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 43.622%	pattern: 3	before: 249	now: 221
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 39.541%	pattern: 4	before: 257	now: 237
+[SOL] flip: 0, stem: 0, fault:239. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 47.194%	pattern: 4	before: 221	now: 207
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 40.051%	pattern: 5	before: 237	now: 235
+[SOL] flip: 0, stem: 0, fault:37. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 49.235%	pattern: 5	before: 207	now: 199
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:439. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 46.684%	pattern: 6	before: 235	now: 209
+[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 49.745%	pattern: 6	before: 199	now: 197
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 60.714%	pattern: 7	before: 209	now: 154
+[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 56.378%	pattern: 7	before: 197	now: 171
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 61.224%	pattern: 8	before: 171	now: 152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:170. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 68.622%	pattern: 9	before: 152	now: 123
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 60.714%	pattern: 7	before: 154	now: 154
+coverage: 68.622%	pattern: 9	before: 123	now: 123
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 60.714%	pattern: 7	before: 154	now: 154
+coverage: 68.622%	pattern: 9	before: 123	now: 123
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:334. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 65.816%	pattern: 8	before: 154	now: 134
+[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 73.980%	pattern: 10	before: 123	now: 102
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 72.959%	pattern: 9	before: 134	now: 106
+[SOL] flip: 0, stem: 0, fault:341. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 78.827%	pattern: 11	before: 102	now: 83
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 75.765%	pattern: 10	before: 106	now: 95
+[SOL] flip: 0, stem: 0, fault:227. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 82.143%	pattern: 12	before: 83	now: 70
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:223. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 79.592%	pattern: 11	before: 95	now: 80
+[SOL] flip: 0, stem: 0, fault:164. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 84.949%	pattern: 13	before: 70	now: 59
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 82.398%	pattern: 12	before: 80	now: 69
+[SOL] flip: 0, stem: 0, fault:255. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 90.561%	pattern: 14	before: 59	now: 37
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 84.949%	pattern: 13	before: 69	now: 59
+[SOL] flip: 0, stem: 0, fault:33. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 91.071%	pattern: 15	before: 37	now: 35
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 86.480%	pattern: 14	before: 59	now: 53
+[SOL] flip: 0, stem: 0, fault:148. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 94.133%	pattern: 16	before: 35	now: 23
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 87.500%	pattern: 15	before: 53	now: 49
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 94.388%	pattern: 17	before: 23	now: 22
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 88.520%	pattern: 16	before: 49	now: 45
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 94.643%	pattern: 18	before: 22	now: 21
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:140. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 90.561%	pattern: 17	before: 45	now: 37
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 94.898%	pattern: 19	before: 21	now: 20
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 91.327%	pattern: 18	before: 37	now: 34
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 94.898%	pattern: 19	before: 20	now: 20
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 91.327%	pattern: 18	before: 34	now: 34
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 94.898%	pattern: 19	before: 20	now: 20
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 91.837%	pattern: 19	before: 34	now: 32
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 94.898%	pattern: 19	before: 20	now: 20
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 93.112%	pattern: 20	before: 32	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 93.112%	pattern: 20	before: 27	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 93.112%	pattern: 20	before: 27	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 93.367%	pattern: 21	before: 27	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 95.663%	pattern: 22	before: 26	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 95.663%	pattern: 22	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 95.918%	pattern: 23	before: 17	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 95.918%	pattern: 23	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 95.918%	pattern: 23	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 97.449%	pattern: 24	before: 16	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 97.449%	pattern: 24	before: 10	now: 10
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 95.663%	pattern: 20	before: 20	now: 17
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 97.449%	pattern: 24	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 97.449%	pattern: 24	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 97.449%	pattern: 24	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 97.449%	pattern: 24	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 97.449%	pattern: 24	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 97.449%	pattern: 24	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 97.449%	pattern: 24	before: 10	now: 10
+coverage: 95.663%	pattern: 20	before: 17	now: 17
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 97.704%	pattern: 25	before: 10	now: 9
+coverage: 95.918%	pattern: 21	before: 17	now: 16
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 97.959%	pattern: 26	before: 9	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 98.724%	pattern: 27	before: 8	now: 5
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 96.684%	pattern: 22	before: 16	now: 13
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 98.724%	pattern: 27	before: 5	now: 5
+coverage: 96.684%	pattern: 22	before: 13	now: 13
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 98.724%	pattern: 27	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 96.939%	pattern: 23	before: 13	now: 12
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 98.724%	pattern: 27	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 97.959%	pattern: 24	before: 12	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 98.724%	pattern: 27	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 98.724%	pattern: 27	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 98.980%	pattern: 28	before: 5	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 98.980%	pattern: 28	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 4	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 98.469%	pattern: 25	before: 8	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 98.469%	pattern: 25	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 98.469%	pattern: 25	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 98.469%	pattern: 25	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 98.469%	pattern: 25	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 98.724%	pattern: 26	before: 6	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 98.980%	pattern: 27	before: 5	now: 4
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 4	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:125
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:125
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:125
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
+coverage: 99.235%	pattern: 28	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:127
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:125
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46
-coverage: 99.235%	pattern: 29	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31
-coverage: 99.235%	pattern: 29	before: 3	now: 3
+coverage: 99.235%	pattern: 28	before: 3	now: 3
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_c499.bench.txt b/exp_result/ATPG-LS_c499.bench.txt
index 0a79198..b301b8d 100644
--- a/exp_result/ATPG-LS_c499.bench.txt
+++ b/exp_result/ATPG-LS_c499.bench.txt
@@ -8,19180 +8,7474 @@ Gate:	243
 Stem:	99
 Level:	5
 ================================ 
-[SOL] flip: 0, stem: 0, fault:1330. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 34.774%	pattern: 1	before: 486	now: 317
+[SOL] flip: 0, stem: 0, fault:1004. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 21.399%	pattern: 1	before: 486	now: 382
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:576. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 43.827%	pattern: 2	before: 317	now: 273
+[SOL] flip: 0, stem: 0, fault:432. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 31.687%	pattern: 2	before: 382	now: 332
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 47.119%	pattern: 3	before: 273	now: 257
+[SOL] flip: 0, stem: 0, fault:82. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 33.745%	pattern: 3	before: 332	now: 322
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 47.942%	pattern: 4	before: 257	now: 253
+[SOL] flip: 0, stem: 0, fault:582. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 40.947%	pattern: 4	before: 322	now: 287
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:817. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 56.790%	pattern: 5	before: 253	now: 210
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 41.975%	pattern: 5	before: 287	now: 282
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 56.790%	pattern: 5	before: 210	now: 210
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 60.905%	pattern: 6	before: 210	now: 190
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 63.374%	pattern: 7	before: 190	now: 178
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 63.374%	pattern: 7	before: 178	now: 178
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:48. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 70.576%	pattern: 8	before: 178	now: 143
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 72.840%	pattern: 9	before: 143	now: 132
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 72.840%	pattern: 9	before: 132	now: 132
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:163. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 74.691%	pattern: 10	before: 132	now: 123
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 78.395%	pattern: 11	before: 123	now: 105
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 78.807%	pattern: 12	before: 105	now: 103
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 80.453%	pattern: 13	before: 103	now: 95
+coverage: 41.975%	pattern: 5	before: 282	now: 282
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 80.453%	pattern: 13	before: 95	now: 95
+coverage: 41.975%	pattern: 5	before: 282	now: 282
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:405. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 47.942%	pattern: 6	before: 282	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 47.942%	pattern: 6	before: 253	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:371. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 56.173%	pattern: 7	before: 253	now: 213
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 56.173%	pattern: 7	before: 213	now: 213
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:646. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 63.169%	pattern: 8	before: 213	now: 179
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:346. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 71.193%	pattern: 9	before: 179	now: 140
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:51. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 72.016%	pattern: 10	before: 140	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 72.016%	pattern: 10	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 72.016%	pattern: 10	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 72.016%	pattern: 10	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 72.016%	pattern: 10	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 72.016%	pattern: 10	before: 136	now: 136
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:40. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 72.634%	pattern: 11	before: 136	now: 133
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:104. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 74.074%	pattern: 12	before: 133	now: 126
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 74.074%	pattern: 12	before: 126	now: 126
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 74.074%	pattern: 12	before: 126	now: 126
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 74.280%	pattern: 13	before: 126	now: 125
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 74.691%	pattern: 14	before: 125	now: 123
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 74.691%	pattern: 14	before: 123	now: 123
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 76.132%	pattern: 15	before: 123	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 76.543%	pattern: 16	before: 116	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 76.543%	pattern: 16	before: 114	now: 114
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:107. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 79.218%	pattern: 17	before: 114	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 79.218%	pattern: 17	before: 101	now: 101
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 80.453%	pattern: 13	before: 95	now: 95
+coverage: 79.218%	pattern: 17	before: 101	now: 101
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 80.453%	pattern: 13	before: 95	now: 95
+[SOL] flip: 0, stem: 0, fault:155. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 81.070%	pattern: 18	before: 101	now: 92
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 80.453%	pattern: 13	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 80.453%	pattern: 13	before: 95	now: 95
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 80.658%	pattern: 14	before: 95	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 80.658%	pattern: 14	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 80.658%	pattern: 14	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 80.658%	pattern: 14	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 80.658%	pattern: 14	before: 94	now: 94
+[SOL] flip: 0, stem: 0, fault:66. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 81.893%	pattern: 19	before: 92	now: 88
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 80.658%	pattern: 14	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 80.658%	pattern: 14	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 80.658%	pattern: 14	before: 94	now: 94
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:34. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 81.687%	pattern: 15	before: 94	now: 89
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 81.687%	pattern: 15	before: 89	now: 89
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 82.099%	pattern: 16	before: 89	now: 87
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 82.922%	pattern: 17	before: 87	now: 83
+coverage: 81.893%	pattern: 19	before: 88	now: 88
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 82.922%	pattern: 17	before: 83	now: 83
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 82.922%	pattern: 17	before: 83	now: 83
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 82.922%	pattern: 17	before: 83	now: 83
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 82.922%	pattern: 17	before: 83	now: 83
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 83.333%	pattern: 18	before: 83	now: 81
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 83.333%	pattern: 18	before: 81	now: 81
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 83.745%	pattern: 19	before: 81	now: 79
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 83.745%	pattern: 19	before: 79	now: 79
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 83.745%	pattern: 19	before: 79	now: 79
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 83.745%	pattern: 19	before: 79	now: 79
+coverage: 81.893%	pattern: 19	before: 88	now: 88
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 84.156%	pattern: 20	before: 79	now: 77
+coverage: 82.305%	pattern: 20	before: 88	now: 86
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 84.568%	pattern: 21	before: 77	now: 75
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 84.979%	pattern: 22	before: 75	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 84.979%	pattern: 22	before: 73	now: 73
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 85.391%	pattern: 23	before: 73	now: 71
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 85.391%	pattern: 23	before: 71	now: 71
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 85.391%	pattern: 23	before: 71	now: 71
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 85.391%	pattern: 23	before: 71	now: 71
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 82.305%	pattern: 20	before: 86	now: 86
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 85.802%	pattern: 24	before: 71	now: 69
+coverage: 82.716%	pattern: 21	before: 86	now: 84
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 85.802%	pattern: 24	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 85.802%	pattern: 24	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 85.802%	pattern: 24	before: 69	now: 69
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 86.626%	pattern: 25	before: 69	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 87.037%	pattern: 26	before: 65	now: 63
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.037%	pattern: 26	before: 63	now: 63
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 87.037%	pattern: 26	before: 63	now: 63
+[SOL] flip: 0, stem: 0, fault:28. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 83.128%	pattern: 22	before: 84	now: 82
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 87.037%	pattern: 26	before: 63	now: 63
+coverage: 83.128%	pattern: 22	before: 82	now: 82
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.037%	pattern: 26	before: 63	now: 63
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 83.128%	pattern: 22	before: 82	now: 82
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.037%	pattern: 26	before: 63	now: 63
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 83.128%	pattern: 22	before: 82	now: 82
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.037%	pattern: 26	before: 63	now: 63
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 87.037%	pattern: 26	before: 63	now: 63
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 87.860%	pattern: 27	before: 63	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 87.860%	pattern: 27	before: 59	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.860%	pattern: 27	before: 59	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.860%	pattern: 27	before: 59	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 87.860%	pattern: 27	before: 59	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.860%	pattern: 27	before: 59	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.860%	pattern: 27	before: 59	now: 59
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 83.539%	pattern: 23	before: 82	now: 80
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 87.860%	pattern: 27	before: 59	now: 59
+coverage: 83.539%	pattern: 23	before: 80	now: 80
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.860%	pattern: 27	before: 59	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 87.860%	pattern: 27	before: 59	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 87.860%	pattern: 27	before: 59	now: 59
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 88.066%	pattern: 28	before: 59	now: 58
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 89.712%	pattern: 29	before: 58	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+coverage: 83.539%	pattern: 23	before: 80	now: 80
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+coverage: 83.539%	pattern: 23	before: 80	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 83.539%	pattern: 23	before: 80	now: 80
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+coverage: 83.539%	pattern: 23	before: 80	now: 80
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+coverage: 83.539%	pattern: 23	before: 80	now: 80
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 84.362%	pattern: 24	before: 80	now: 76
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+coverage: 84.362%	pattern: 24	before: 76	now: 76
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 84.774%	pattern: 25	before: 76	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 89.712%	pattern: 29	before: 50	now: 50
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 89.712%	pattern: 29	before: 50	now: 50
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:151. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 91.358%	pattern: 30	before: 50	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 84.774%	pattern: 25	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 84.774%	pattern: 25	before: 74	now: 74
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 85.185%	pattern: 26	before: 74	now: 72
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 85.185%	pattern: 26	before: 72	now: 72
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 85.185%	pattern: 26	before: 72	now: 72
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 85.185%	pattern: 26	before: 72	now: 72
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 85.185%	pattern: 26	before: 72	now: 72
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 85.185%	pattern: 26	before: 72	now: 72
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 85.185%	pattern: 26	before: 72	now: 72
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
+coverage: 85.185%	pattern: 26	before: 72	now: 72
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 85.185%	pattern: 26	before: 72	now: 72
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 85.597%	pattern: 27	before: 72	now: 70
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 85.597%	pattern: 27	before: 70	now: 70
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 85.597%	pattern: 27	before: 70	now: 70
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 86.008%	pattern: 28	before: 70	now: 68
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 86.008%	pattern: 28	before: 68	now: 68
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 86.008%	pattern: 28	before: 68	now: 68
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 86.008%	pattern: 28	before: 68	now: 68
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:126. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 87.654%	pattern: 29	before: 68	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 87.654%	pattern: 29	before: 60	now: 60
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 88.066%	pattern: 30	before: 60	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 88.066%	pattern: 30	before: 58	now: 58
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 88.066%	pattern: 30	before: 58	now: 58
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:100. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 89.712%	pattern: 31	before: 58	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 89.712%	pattern: 31	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 89.712%	pattern: 31	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:91. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 90.741%	pattern: 32	before: 50	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:136. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 92.387%	pattern: 33	before: 45	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 91.358%	pattern: 30	before: 42	now: 42
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 93.004%	pattern: 31	before: 42	now: 34
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 93.004%	pattern: 31	before: 34	now: 34
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 93.827%	pattern: 32	before: 34	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.387%	pattern: 33	before: 37	now: 37
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 92.387%	pattern: 33	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 92.387%	pattern: 33	before: 37	now: 37
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 92.798%	pattern: 34	before: 37	now: 35
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 93.827%	pattern: 32	before: 30	now: 30
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 92.798%	pattern: 34	before: 35	now: 35
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 93.827%	pattern: 35	before: 35	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 93.827%	pattern: 35	before: 30	now: 30
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 94.033%	pattern: 36	before: 30	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 94.033%	pattern: 36	before: 29	now: 29
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 94.033%	pattern: 36	before: 29	now: 29
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 94.650%	pattern: 33	before: 30	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 94.650%	pattern: 33	before: 26	now: 26
+coverage: 94.856%	pattern: 37	before: 29	now: 25
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
+coverage: 94.856%	pattern: 37	before: 25	now: 25
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 94.650%	pattern: 33	before: 26	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 95.679%	pattern: 34	before: 26	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 95.679%	pattern: 34	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 95.679%	pattern: 34	before: 21	now: 21
+coverage: 94.856%	pattern: 37	before: 25	now: 25
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 95.885%	pattern: 35	before: 21	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 95.885%	pattern: 35	before: 20	now: 20
+coverage: 95.062%	pattern: 38	before: 25	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 95.885%	pattern: 35	before: 20	now: 20
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 95.885%	pattern: 35	before: 20	now: 20
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.091%	pattern: 36	before: 20	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.091%	pattern: 36	before: 19	now: 19
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 96.296%	pattern: 37	before: 19	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 96.296%	pattern: 37	before: 18	now: 18
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 96.296%	pattern: 37	before: 18	now: 18
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.296%	pattern: 37	before: 18	now: 18
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.296%	pattern: 37	before: 18	now: 18
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.296%	pattern: 37	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.502%	pattern: 38	before: 18	now: 17
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 95.062%	pattern: 38	before: 24	now: 24
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 95.062%	pattern: 38	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 95.062%	pattern: 38	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 95.062%	pattern: 38	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 95.062%	pattern: 38	before: 24	now: 24
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 95.267%	pattern: 39	before: 24	now: 23
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.502%	pattern: 38	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.708%	pattern: 39	before: 17	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.708%	pattern: 39	before: 16	now: 16
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 96.914%	pattern: 40	before: 16	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 96.914%	pattern: 40	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 97.119%	pattern: 41	before: 15	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 97.119%	pattern: 41	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 97.325%	pattern: 42	before: 14	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.325%	pattern: 42	before: 13	now: 13
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 97.531%	pattern: 43	before: 13	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.531%	pattern: 43	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.531%	pattern: 43	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.531%	pattern: 43	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.531%	pattern: 43	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.531%	pattern: 43	before: 12	now: 12
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 97.737%	pattern: 44	before: 12	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.737%	pattern: 44	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 97.942%	pattern: 45	before: 11	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 97.942%	pattern: 45	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 98.148%	pattern: 46	before: 10	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.148%	pattern: 46	before: 9	now: 9
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.354%	pattern: 47	before: 9	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 98.354%	pattern: 47	before: 8	now: 8
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.560%	pattern: 48	before: 8	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.560%	pattern: 48	before: 7	now: 7
+coverage: 95.267%	pattern: 39	before: 23	now: 23
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
+coverage: 95.267%	pattern: 39	before: 23	now: 23
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
+coverage: 95.267%	pattern: 39	before: 23	now: 23
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
+coverage: 95.267%	pattern: 39	before: 23	now: 23
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.560%	pattern: 48	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.560%	pattern: 48	before: 7	now: 7
+coverage: 95.267%	pattern: 39	before: 23	now: 23
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.765%	pattern: 49	before: 7	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
+coverage: 95.473%	pattern: 40	before: 23	now: 22
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 98.765%	pattern: 49	before: 6	now: 6
+coverage: 95.473%	pattern: 40	before: 22	now: 22
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.765%	pattern: 49	before: 6	now: 6
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 95.473%	pattern: 40	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 95.473%	pattern: 40	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 95.473%	pattern: 40	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 95.473%	pattern: 40	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 95.473%	pattern: 40	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 95.473%	pattern: 40	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 95.473%	pattern: 40	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:62. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 96.296%	pattern: 41	before: 22	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.296%	pattern: 41	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 96.296%	pattern: 41	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.296%	pattern: 41	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 96.296%	pattern: 41	before: 18	now: 18
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 96.296%	pattern: 41	before: 18	now: 18
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.765%	pattern: 49	before: 6	now: 6
+coverage: 96.296%	pattern: 41	before: 18	now: 18
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.765%	pattern: 49	before: 6	now: 6
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.296%	pattern: 41	before: 18	now: 18
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 98.765%	pattern: 49	before: 6	now: 6
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 96.296%	pattern: 41	before: 18	now: 18
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.971%	pattern: 50	before: 6	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.296%	pattern: 41	before: 18	now: 18
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 96.502%	pattern: 42	before: 18	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 96.502%	pattern: 42	before: 17	now: 17
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 96.502%	pattern: 42	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 96.708%	pattern: 43	before: 17	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 96.708%	pattern: 43	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.708%	pattern: 43	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 96.708%	pattern: 43	before: 16	now: 16
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 96.914%	pattern: 44	before: 16	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 96.914%	pattern: 44	before: 15	now: 15
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.119%	pattern: 45	before: 15	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.119%	pattern: 45	before: 14	now: 14
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 97.325%	pattern: 46	before: 14	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.325%	pattern: 46	before: 13	now: 13
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 97.531%	pattern: 47	before: 13	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.531%	pattern: 47	before: 12	now: 12
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:14. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.737%	pattern: 48	before: 12	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.737%	pattern: 48	before: 11	now: 11
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.942%	pattern: 49	before: 11	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 97.942%	pattern: 49	before: 10	now: 10
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 98.148%	pattern: 50	before: 10	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.148%	pattern: 50	before: 9	now: 9
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 98.354%	pattern: 51	before: 9	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 98.971%	pattern: 50	before: 5	now: 5
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 98.971%	pattern: 50	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.177%	pattern: 51	before: 5	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.177%	pattern: 51	before: 4	now: 4
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.177%	pattern: 51	before: 4	now: 4
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 4	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.354%	pattern: 51	before: 8	now: 8
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 98.354%	pattern: 51	before: 8	now: 8
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 98.560%	pattern: 52	before: 8	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.383%	pattern: 52	before: 3	now: 3
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.560%	pattern: 52	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.765%	pattern: 53	before: 7	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.765%	pattern: 53	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.971%	pattern: 54	before: 6	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 98.971%	pattern: 54	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.177%	pattern: 55	before: 5	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.177%	pattern: 55	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.383%	pattern: 56	before: 4	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.383%	pattern: 56	before: 3	now: 3
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.383%	pattern: 56	before: 3	now: 3
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 3	now: 2
+coverage: 99.588%	pattern: 57	before: 3	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.588%	pattern: 53	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 2	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:199
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.588%	pattern: 57	before: 2	now: 2
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.588%	pattern: 57	before: 2	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.794%	pattern: 58	before: 2	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
-coverage: 99.794%	pattern: 54	before: 1	now: 1
+coverage: 99.794%	pattern: 58	before: 1	now: 1
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
-coverage: 100.000%	pattern: 55	before: 1	now: 0
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104
+coverage: 99.794%	pattern: 58	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 99, fault_cnt:200
+coverage: 100.000%	pattern: 59	before: 1	now: 0
 checking valid circuit ... result: 1.
 
-real	9m9.017s
-user	9m8.925s
-sys	0m0.056s
+real	1m12.889s
+user	1m12.883s
+sys	0m0.000s
diff --git a/exp_result/ATPG-LS_c5315.bench.txt b/exp_result/ATPG-LS_c5315.bench.txt
index a4f6bb3..d658c30 100644
--- a/exp_result/ATPG-LS_c5315.bench.txt
+++ b/exp_result/ATPG-LS_c5315.bench.txt
@@ -8,3 +8,2427 @@ Gate:	2485
 Stem:	984
 Level:	10
 ================================ 
+[SOL] flip: 0, stem: 0, fault:10765. flip_cnt: 0, stem_cnt: 984, fault_cnt:802
+coverage: 16.137%	pattern: 1	before: 4970	now: 4168
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:7281. flip_cnt: 0, stem_cnt: 984, fault_cnt:788
+coverage: 24.527%	pattern: 2	before: 4168	now: 3751
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:4076. flip_cnt: 0, stem_cnt: 984, fault_cnt:659
+coverage: 29.296%	pattern: 3	before: 3751	now: 3514
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3188. flip_cnt: 0, stem_cnt: 984, fault_cnt:818
+coverage: 34.085%	pattern: 4	before: 3514	now: 3276
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1372. flip_cnt: 0, stem_cnt: 984, fault_cnt:804
+coverage: 35.734%	pattern: 5	before: 3276	now: 3194
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:724. flip_cnt: 0, stem_cnt: 984, fault_cnt:793
+coverage: 36.720%	pattern: 6	before: 3194	now: 3145
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6959. flip_cnt: 0, stem_cnt: 984, fault_cnt:1089
+coverage: 44.386%	pattern: 7	before: 3145	now: 2764
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:348. flip_cnt: 0, stem_cnt: 984, fault_cnt:804
+coverage: 44.950%	pattern: 8	before: 2764	now: 2736
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:499. flip_cnt: 0, stem_cnt: 984, fault_cnt:779
+coverage: 45.594%	pattern: 9	before: 2736	now: 2704
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3610. flip_cnt: 0, stem_cnt: 984, fault_cnt:928
+coverage: 49.416%	pattern: 10	before: 2704	now: 2514
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:9044. flip_cnt: 0, stem_cnt: 984, fault_cnt:1156
+coverage: 58.994%	pattern: 11	before: 2514	now: 2038
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 984, fault_cnt:807
+coverage: 59.215%	pattern: 12	before: 2038	now: 2027
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 984, fault_cnt:624
+coverage: 59.437%	pattern: 13	before: 2027	now: 2016
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6080. flip_cnt: 0, stem_cnt: 984, fault_cnt:1245
+coverage: 65.875%	pattern: 14	before: 2016	now: 1696
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:690
+coverage: 65.915%	pattern: 15	before: 1696	now: 1694
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 984, fault_cnt:725
+coverage: 66.237%	pattern: 16	before: 1694	now: 1678
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3382. flip_cnt: 0, stem_cnt: 984, fault_cnt:976
+coverage: 69.819%	pattern: 17	before: 1678	now: 1500
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 984, fault_cnt:785
+coverage: 70.141%	pattern: 18	before: 1500	now: 1484
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:3781. flip_cnt: 0, stem_cnt: 984, fault_cnt:1218
+coverage: 74.145%	pattern: 19	before: 1484	now: 1285
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1767. flip_cnt: 0, stem_cnt: 984, fault_cnt:1008
+coverage: 76.016%	pattern: 20	before: 1285	now: 1192
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 984, fault_cnt:673
+coverage: 76.137%	pattern: 21	before: 1192	now: 1186
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 984, fault_cnt:788
+coverage: 76.539%	pattern: 22	before: 1186	now: 1166
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:666
+coverage: 76.579%	pattern: 23	before: 1166	now: 1164
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:67. flip_cnt: 0, stem_cnt: 984, fault_cnt:641
+coverage: 76.660%	pattern: 24	before: 1164	now: 1160
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:806
+coverage: 76.720%	pattern: 25	before: 1160	now: 1157
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:788
+coverage: 76.781%	pattern: 26	before: 1157	now: 1154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:761
+coverage: 76.781%	pattern: 26	before: 1154	now: 1154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:769
+coverage: 76.781%	pattern: 26	before: 1154	now: 1154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:657
+coverage: 76.781%	pattern: 26	before: 1154	now: 1154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:818
+coverage: 76.821%	pattern: 27	before: 1154	now: 1152
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 984, fault_cnt:717
+coverage: 77.183%	pattern: 28	before: 1152	now: 1134
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 984, fault_cnt:871
+coverage: 77.304%	pattern: 29	before: 1134	now: 1128
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 984, fault_cnt:866
+coverage: 77.404%	pattern: 30	before: 1128	now: 1123
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:703. flip_cnt: 0, stem_cnt: 984, fault_cnt:944
+coverage: 78.149%	pattern: 31	before: 1123	now: 1086
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:2565. flip_cnt: 0, stem_cnt: 984, fault_cnt:1152
+coverage: 80.865%	pattern: 32	before: 1086	now: 951
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:741
+coverage: 80.865%	pattern: 32	before: 951	now: 951
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 984, fault_cnt:844
+coverage: 81.187%	pattern: 33	before: 951	now: 935
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 984, fault_cnt:846
+coverage: 81.549%	pattern: 34	before: 935	now: 917
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:755
+coverage: 81.610%	pattern: 35	before: 917	now: 914
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:704
+coverage: 81.610%	pattern: 35	before: 914	now: 914
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:662
+coverage: 81.610%	pattern: 35	before: 914	now: 914
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:589. flip_cnt: 0, stem_cnt: 984, fault_cnt:944
+coverage: 82.233%	pattern: 36	before: 914	now: 883
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:773
+coverage: 82.233%	pattern: 36	before: 883	now: 883
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:684. flip_cnt: 0, stem_cnt: 984, fault_cnt:1119
+coverage: 82.958%	pattern: 37	before: 883	now: 847
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:816
+coverage: 83.038%	pattern: 38	before: 847	now: 843
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 984, fault_cnt:771
+coverage: 83.159%	pattern: 39	before: 843	now: 837
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:683
+coverage: 83.159%	pattern: 39	before: 837	now: 837
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:2584. flip_cnt: 0, stem_cnt: 984, fault_cnt:1160
+coverage: 85.895%	pattern: 40	before: 837	now: 701
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:778
+coverage: 85.895%	pattern: 40	before: 701	now: 701
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:895
+coverage: 85.956%	pattern: 41	before: 701	now: 698
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:687
+coverage: 85.956%	pattern: 41	before: 698	now: 698
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:705
+coverage: 85.956%	pattern: 41	before: 698	now: 698
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:33. flip_cnt: 0, stem_cnt: 984, fault_cnt:812
+coverage: 86.016%	pattern: 42	before: 698	now: 695
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:708
+coverage: 86.056%	pattern: 43	before: 695	now: 693
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:681
+coverage: 86.056%	pattern: 43	before: 693	now: 693
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:646. flip_cnt: 0, stem_cnt: 984, fault_cnt:1180
+coverage: 86.740%	pattern: 44	before: 693	now: 659
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:728
+coverage: 86.740%	pattern: 44	before: 659	now: 659
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:696
+coverage: 86.761%	pattern: 45	before: 659	now: 658
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1064. flip_cnt: 0, stem_cnt: 984, fault_cnt:1109
+coverage: 87.887%	pattern: 46	before: 658	now: 602
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:661
+coverage: 87.887%	pattern: 46	before: 602	now: 602
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 984, fault_cnt:1249
+coverage: 88.229%	pattern: 47	before: 602	now: 585
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:659
+coverage: 88.229%	pattern: 47	before: 585	now: 585
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:771
+coverage: 88.270%	pattern: 48	before: 585	now: 583
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 984, fault_cnt:1111
+coverage: 89.296%	pattern: 49	before: 583	now: 532
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:698
+coverage: 89.296%	pattern: 49	before: 532	now: 532
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:792
+coverage: 89.296%	pattern: 49	before: 532	now: 532
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 984, fault_cnt:779
+coverage: 89.396%	pattern: 50	before: 532	now: 527
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:668
+coverage: 89.396%	pattern: 50	before: 527	now: 527
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:698
+coverage: 89.396%	pattern: 50	before: 527	now: 527
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:688
+coverage: 89.396%	pattern: 50	before: 527	now: 527
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:795
+coverage: 89.477%	pattern: 51	before: 527	now: 523
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:668
+coverage: 89.477%	pattern: 51	before: 523	now: 523
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:676
+coverage: 89.477%	pattern: 51	before: 523	now: 523
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:802
+coverage: 89.477%	pattern: 51	before: 523	now: 523
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:775
+coverage: 89.477%	pattern: 51	before: 523	now: 523
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:849
+coverage: 89.517%	pattern: 52	before: 523	now: 521
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:737
+coverage: 89.577%	pattern: 53	before: 521	now: 518
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:715
+coverage: 89.658%	pattern: 54	before: 518	now: 514
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:637
+coverage: 89.698%	pattern: 55	before: 514	now: 512
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:681
+coverage: 89.698%	pattern: 55	before: 512	now: 512
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:1140. flip_cnt: 0, stem_cnt: 984, fault_cnt:1160
+coverage: 90.905%	pattern: 56	before: 512	now: 452
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:627. flip_cnt: 0, stem_cnt: 984, fault_cnt:1265
+coverage: 91.569%	pattern: 57	before: 452	now: 419
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 984, fault_cnt:948
+coverage: 92.032%	pattern: 58	before: 419	now: 396
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:811
+coverage: 92.032%	pattern: 58	before: 396	now: 396
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 984, fault_cnt:1056
+coverage: 92.334%	pattern: 59	before: 396	now: 381
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:1053
+coverage: 92.414%	pattern: 60	before: 381	now: 377
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:691
+coverage: 92.414%	pattern: 60	before: 377	now: 377
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:821
+coverage: 92.414%	pattern: 60	before: 377	now: 377
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:785
+coverage: 92.414%	pattern: 60	before: 377	now: 377
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 984, fault_cnt:931
+coverage: 92.555%	pattern: 61	before: 377	now: 370
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:692
+coverage: 92.575%	pattern: 62	before: 370	now: 369
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:777
+coverage: 92.596%	pattern: 63	before: 369	now: 368
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:753
+coverage: 92.596%	pattern: 63	before: 368	now: 368
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 984, fault_cnt:1098
+coverage: 92.736%	pattern: 64	before: 368	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:655
+coverage: 92.736%	pattern: 64	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:688
+coverage: 92.736%	pattern: 64	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:660
+coverage: 92.736%	pattern: 64	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 984, fault_cnt:757
+coverage: 92.857%	pattern: 65	before: 361	now: 355
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:803
+coverage: 92.857%	pattern: 65	before: 355	now: 355
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:668
+coverage: 92.877%	pattern: 66	before: 355	now: 354
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:804
+coverage: 92.877%	pattern: 66	before: 354	now: 354
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:770
+coverage: 92.897%	pattern: 67	before: 354	now: 353
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:671
+coverage: 92.897%	pattern: 67	before: 353	now: 353
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:677
+coverage: 92.918%	pattern: 68	before: 353	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:645
+coverage: 92.918%	pattern: 68	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:798
+coverage: 92.918%	pattern: 68	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:806
+coverage: 92.918%	pattern: 68	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:784
+coverage: 92.918%	pattern: 68	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:794
+coverage: 92.918%	pattern: 68	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:630
+coverage: 92.918%	pattern: 68	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:710
+coverage: 92.918%	pattern: 68	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 984, fault_cnt:1224
+coverage: 93.280%	pattern: 69	before: 352	now: 334
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:776
+coverage: 93.280%	pattern: 69	before: 334	now: 334
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:665
+coverage: 93.280%	pattern: 69	before: 334	now: 334
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:669
+coverage: 93.280%	pattern: 69	before: 334	now: 334
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:760
+coverage: 93.300%	pattern: 70	before: 334	now: 333
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:680
+coverage: 93.300%	pattern: 70	before: 333	now: 333
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:768
+coverage: 93.300%	pattern: 70	before: 333	now: 333
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:699
+coverage: 93.300%	pattern: 70	before: 333	now: 333
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:664
+coverage: 93.300%	pattern: 70	before: 333	now: 333
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 984, fault_cnt:968
+coverage: 93.581%	pattern: 71	before: 333	now: 319
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:676
+coverage: 93.581%	pattern: 71	before: 319	now: 319
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:654
+coverage: 93.581%	pattern: 71	before: 319	now: 319
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:782
+coverage: 93.581%	pattern: 71	before: 319	now: 319
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:650
+coverage: 93.581%	pattern: 71	before: 319	now: 319
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 984, fault_cnt:980
+coverage: 93.783%	pattern: 72	before: 319	now: 309
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:1007
+coverage: 93.863%	pattern: 73	before: 309	now: 305
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:760
+coverage: 93.863%	pattern: 73	before: 305	now: 305
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:631
+coverage: 93.863%	pattern: 73	before: 305	now: 305
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:797
+coverage: 93.863%	pattern: 73	before: 305	now: 305
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:589. flip_cnt: 0, stem_cnt: 984, fault_cnt:1232
+coverage: 94.487%	pattern: 74	before: 305	now: 274
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:792
+coverage: 94.507%	pattern: 75	before: 274	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:786
+coverage: 94.507%	pattern: 75	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:822
+coverage: 94.507%	pattern: 75	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:677
+coverage: 94.507%	pattern: 75	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:861
+coverage: 94.507%	pattern: 75	before: 273	now: 273
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1107
+coverage: 94.547%	pattern: 76	before: 273	now: 271
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:691
+coverage: 94.547%	pattern: 76	before: 271	now: 271
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:1028
+coverage: 94.608%	pattern: 77	before: 271	now: 268
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1034
+coverage: 94.648%	pattern: 78	before: 268	now: 266
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:715
+coverage: 94.648%	pattern: 78	before: 266	now: 266
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:818
+coverage: 94.648%	pattern: 78	before: 266	now: 266
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:692
+coverage: 94.648%	pattern: 78	before: 266	now: 266
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:674
+coverage: 94.648%	pattern: 78	before: 266	now: 266
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 984, fault_cnt:984
+coverage: 94.748%	pattern: 79	before: 266	now: 261
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:799
+coverage: 94.748%	pattern: 79	before: 261	now: 261
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:756
+coverage: 94.748%	pattern: 79	before: 261	now: 261
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:829
+coverage: 94.748%	pattern: 79	before: 261	now: 261
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:885
+coverage: 94.748%	pattern: 79	before: 261	now: 261
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:807
+coverage: 94.748%	pattern: 79	before: 261	now: 261
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:753
+coverage: 94.748%	pattern: 79	before: 261	now: 261
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 984, fault_cnt:1052
+coverage: 94.889%	pattern: 80	before: 261	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:656
+coverage: 94.889%	pattern: 80	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:757
+coverage: 94.889%	pattern: 80	before: 254	now: 254
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:829
+coverage: 94.909%	pattern: 81	before: 254	now: 253
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1075
+coverage: 94.950%	pattern: 82	before: 253	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:665
+coverage: 94.950%	pattern: 82	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1044
+coverage: 94.950%	pattern: 82	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:754
+coverage: 94.950%	pattern: 82	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:772
+coverage: 94.950%	pattern: 82	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:697
+coverage: 94.950%	pattern: 82	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:964
+coverage: 94.950%	pattern: 82	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:675
+coverage: 94.950%	pattern: 82	before: 251	now: 251
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 984, fault_cnt:1138
+coverage: 95.292%	pattern: 83	before: 251	now: 234
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:806
+coverage: 95.292%	pattern: 83	before: 234	now: 234
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:939
+coverage: 95.332%	pattern: 84	before: 234	now: 232
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:930
+coverage: 95.352%	pattern: 85	before: 232	now: 231
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:839
+coverage: 95.352%	pattern: 85	before: 231	now: 231
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:820
+coverage: 95.352%	pattern: 85	before: 231	now: 231
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:675
+coverage: 95.352%	pattern: 85	before: 231	now: 231
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:838
+coverage: 95.372%	pattern: 86	before: 231	now: 230
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:773
+coverage: 95.392%	pattern: 87	before: 230	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:743
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:807
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:794
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:653
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:646
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:842
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:761
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:976
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:706
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:961
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:670
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:793
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:694
+coverage: 95.392%	pattern: 87	before: 229	now: 229
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1064
+coverage: 95.412%	pattern: 88	before: 229	now: 228
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:741
+coverage: 95.412%	pattern: 88	before: 228	now: 228
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:733
+coverage: 95.412%	pattern: 88	before: 228	now: 228
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:685
+coverage: 95.412%	pattern: 88	before: 228	now: 228
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:787
+coverage: 95.412%	pattern: 88	before: 228	now: 228
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:668
+coverage: 95.412%	pattern: 88	before: 228	now: 228
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:757
+coverage: 95.433%	pattern: 89	before: 228	now: 227
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:754
+coverage: 95.433%	pattern: 89	before: 227	now: 227
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:785
+coverage: 95.433%	pattern: 89	before: 227	now: 227
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:782
+coverage: 95.433%	pattern: 89	before: 227	now: 227
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:699
+coverage: 95.433%	pattern: 89	before: 227	now: 227
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:742
+coverage: 95.433%	pattern: 89	before: 227	now: 227
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:676
+coverage: 95.433%	pattern: 89	before: 227	now: 227
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 984, fault_cnt:1301
+coverage: 95.674%	pattern: 90	before: 227	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:753
+coverage: 95.674%	pattern: 90	before: 215	now: 215
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:655
+coverage: 95.694%	pattern: 91	before: 215	now: 214
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:818
+coverage: 95.694%	pattern: 91	before: 214	now: 214
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:666
+coverage: 95.694%	pattern: 91	before: 214	now: 214
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 984, fault_cnt:1273
+coverage: 96.137%	pattern: 92	before: 214	now: 192
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:1150
+coverage: 96.217%	pattern: 93	before: 192	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:774
+coverage: 96.217%	pattern: 93	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:841
+coverage: 96.217%	pattern: 93	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:762
+coverage: 96.217%	pattern: 93	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:775
+coverage: 96.217%	pattern: 93	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1063
+coverage: 96.217%	pattern: 93	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:687
+coverage: 96.217%	pattern: 93	before: 188	now: 188
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 984, fault_cnt:1277
+coverage: 96.519%	pattern: 94	before: 188	now: 173
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:813
+coverage: 96.519%	pattern: 94	before: 173	now: 173
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:683
+coverage: 96.519%	pattern: 94	before: 173	now: 173
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:737
+coverage: 96.519%	pattern: 94	before: 173	now: 173
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1036
+coverage: 96.539%	pattern: 95	before: 173	now: 172
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:646
+coverage: 96.539%	pattern: 95	before: 172	now: 172
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:818
+coverage: 96.539%	pattern: 95	before: 172	now: 172
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:681
+coverage: 96.539%	pattern: 95	before: 172	now: 172
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:973
+coverage: 96.539%	pattern: 95	before: 172	now: 172
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 984, fault_cnt:1286
+coverage: 96.720%	pattern: 96	before: 172	now: 163
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 984, fault_cnt:1166
+coverage: 96.901%	pattern: 97	before: 163	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:837
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:785
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:674
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:792
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:684
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:956
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:786
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:786
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:712
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:805
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:641
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:819
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:807
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:740
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:676
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:996
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:804
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1244
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:681
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:988
+coverage: 96.901%	pattern: 97	before: 154	now: 154
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 984, fault_cnt:1162
+coverage: 97.304%	pattern: 98	before: 154	now: 134
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1031
+coverage: 97.344%	pattern: 99	before: 134	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:947
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:686
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:630
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1055
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:792
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:783
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:766
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:675
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:678
+coverage: 97.344%	pattern: 99	before: 132	now: 132
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 984, fault_cnt:1338
+coverage: 97.606%	pattern: 100	before: 132	now: 119
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1060
+coverage: 97.646%	pattern: 101	before: 119	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:766
+coverage: 97.646%	pattern: 101	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:773
+coverage: 97.646%	pattern: 101	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:744
+coverage: 97.646%	pattern: 101	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:743
+coverage: 97.646%	pattern: 101	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:787
+coverage: 97.646%	pattern: 101	before: 117	now: 117
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1169
+coverage: 97.666%	pattern: 102	before: 117	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:791
+coverage: 97.666%	pattern: 102	before: 116	now: 116
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:1234
+coverage: 97.746%	pattern: 103	before: 116	now: 112
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:658
+coverage: 97.746%	pattern: 103	before: 112	now: 112
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:805
+coverage: 97.746%	pattern: 103	before: 112	now: 112
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1151
+coverage: 97.767%	pattern: 104	before: 112	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:763
+coverage: 97.767%	pattern: 104	before: 111	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:810
+coverage: 97.767%	pattern: 104	before: 111	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:785
+coverage: 97.767%	pattern: 104	before: 111	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:794
+coverage: 97.767%	pattern: 104	before: 111	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:768
+coverage: 97.767%	pattern: 104	before: 111	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:716
+coverage: 97.767%	pattern: 104	before: 111	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:692
+coverage: 97.767%	pattern: 104	before: 111	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:649
+coverage: 97.767%	pattern: 104	before: 111	now: 111
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:1147
+coverage: 97.847%	pattern: 105	before: 111	now: 107
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:769
+coverage: 97.847%	pattern: 105	before: 107	now: 107
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:794
+coverage: 97.847%	pattern: 105	before: 107	now: 107
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1052
+coverage: 97.867%	pattern: 106	before: 107	now: 106
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:737
+coverage: 97.867%	pattern: 106	before: 106	now: 106
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:675
+coverage: 97.867%	pattern: 106	before: 106	now: 106
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:1204
+coverage: 97.928%	pattern: 107	before: 106	now: 103
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:912
+coverage: 97.928%	pattern: 107	before: 103	now: 103
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:696
+coverage: 97.928%	pattern: 107	before: 103	now: 103
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:814
+coverage: 97.928%	pattern: 107	before: 103	now: 103
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:827
+coverage: 97.928%	pattern: 107	before: 103	now: 103
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:825
+coverage: 97.928%	pattern: 107	before: 103	now: 103
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:993
+coverage: 97.968%	pattern: 108	before: 103	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1137
+coverage: 97.968%	pattern: 108	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:652
+coverage: 97.968%	pattern: 108	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:680
+coverage: 97.968%	pattern: 108	before: 101	now: 101
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1079
+coverage: 97.988%	pattern: 109	before: 101	now: 100
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:735
+coverage: 97.988%	pattern: 109	before: 100	now: 100
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:695
+coverage: 97.988%	pattern: 109	before: 100	now: 100
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:775
+coverage: 98.008%	pattern: 110	before: 100	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:766
+coverage: 98.008%	pattern: 110	before: 99	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:678
+coverage: 98.008%	pattern: 110	before: 99	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:713
+coverage: 98.008%	pattern: 110	before: 99	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:734
+coverage: 98.008%	pattern: 110	before: 99	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:840
+coverage: 98.008%	pattern: 110	before: 99	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:752
+coverage: 98.008%	pattern: 110	before: 99	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:738
+coverage: 98.008%	pattern: 110	before: 99	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:819
+coverage: 98.008%	pattern: 110	before: 99	now: 99
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1381
+coverage: 98.048%	pattern: 111	before: 99	now: 97
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:801
+coverage: 98.048%	pattern: 111	before: 97	now: 97
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:673
+coverage: 98.048%	pattern: 111	before: 97	now: 97
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:702
+coverage: 98.048%	pattern: 111	before: 97	now: 97
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:797
+coverage: 98.048%	pattern: 111	before: 97	now: 97
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1272
+coverage: 98.068%	pattern: 112	before: 97	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:763
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:793
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:789
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:915
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:754
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:645
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:772
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:737
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:649
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:656
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:705
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:766
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:817
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:817
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:674
+coverage: 98.068%	pattern: 112	before: 96	now: 96
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:670
+coverage: 98.089%	pattern: 113	before: 96	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:654
+coverage: 98.089%	pattern: 113	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1104
+coverage: 98.089%	pattern: 113	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:688
+coverage: 98.089%	pattern: 113	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:617
+coverage: 98.089%	pattern: 113	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:669
+coverage: 98.089%	pattern: 113	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:729
+coverage: 98.089%	pattern: 113	before: 95	now: 95
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:1138
+coverage: 98.169%	pattern: 114	before: 95	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:724
+coverage: 98.169%	pattern: 114	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:738
+coverage: 98.169%	pattern: 114	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:987
+coverage: 98.169%	pattern: 114	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:776
+coverage: 98.169%	pattern: 114	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:816
+coverage: 98.169%	pattern: 114	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:827
+coverage: 98.169%	pattern: 114	before: 91	now: 91
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1145
+coverage: 98.189%	pattern: 115	before: 91	now: 90
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:704
+coverage: 98.189%	pattern: 115	before: 90	now: 90
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:721
+coverage: 98.189%	pattern: 115	before: 90	now: 90
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1043
+coverage: 98.189%	pattern: 115	before: 90	now: 90
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1285
+coverage: 98.229%	pattern: 116	before: 90	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1353
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:907
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:698
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:674
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:807
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:847
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:772
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:694
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:699
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:774
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:682
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:767
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:669
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:782
+coverage: 98.229%	pattern: 116	before: 88	now: 88
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 984, fault_cnt:1145
+coverage: 98.330%	pattern: 117	before: 88	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:745
+coverage: 98.330%	pattern: 117	before: 83	now: 83
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1250
+coverage: 98.370%	pattern: 118	before: 83	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:701
+coverage: 98.370%	pattern: 118	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:704
+coverage: 98.370%	pattern: 118	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:795
+coverage: 98.370%	pattern: 118	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:776
+coverage: 98.370%	pattern: 118	before: 81	now: 81
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:685
+coverage: 98.390%	pattern: 119	before: 81	now: 80
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:1276
+coverage: 98.471%	pattern: 120	before: 80	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:701
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:803
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:901
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:664
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:795
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:784
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:681
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:789
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:817
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:785
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:733
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:809
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:678
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:812
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1096
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:932
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:786
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:797
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:683
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:768
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:684
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1268
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:859
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1158
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:779
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1062
+coverage: 98.471%	pattern: 120	before: 76	now: 76
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1052
+coverage: 98.511%	pattern: 121	before: 76	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:738
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:760
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:767
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:829
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:653
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:805
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:674
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:982
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1262
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1155
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:705
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1061
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:662
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:706
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:784
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:767
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:803
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:642
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:797
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:802
+coverage: 98.511%	pattern: 121	before: 74	now: 74
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:1262
+coverage: 98.571%	pattern: 122	before: 74	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:779
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:754
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:821
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:979
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1158
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:695
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:639
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:685
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:824
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:740
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:813
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:759
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:665
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:655
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:932
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:858
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:670
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:753
+coverage: 98.571%	pattern: 122	before: 71	now: 71
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:785
+coverage: 98.592%	pattern: 123	before: 71	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:671
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:808
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:762
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:767
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:632
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:686
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:802
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:683
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:855
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1107
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:775
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:614
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:825
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1002
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:776
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:876
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:815
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:948
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:772
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:717
+coverage: 98.592%	pattern: 123	before: 70	now: 70
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 984, fault_cnt:1275
+coverage: 98.672%	pattern: 124	before: 70	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:786
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:703
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:749
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:977
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1244
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:670
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:764
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:795
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:678
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:970
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:784
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:827
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:815
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:792
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:646
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1129
+coverage: 98.672%	pattern: 124	before: 66	now: 66
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1135
+coverage: 98.692%	pattern: 125	before: 66	now: 65
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:871
+coverage: 98.692%	pattern: 125	before: 65	now: 65
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:796
+coverage: 98.692%	pattern: 125	before: 65	now: 65
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:654
+coverage: 98.692%	pattern: 125	before: 65	now: 65
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1123
+coverage: 98.732%	pattern: 126	before: 65	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:785
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:771
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:682
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:825
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:679
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:662
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:648
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:839
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1025
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:702
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:810
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:659
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:768
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:774
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:944
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:985
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:863
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:774
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:768
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1065
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:646
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1096
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:773
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1045
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1077
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:867
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:765
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:826
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:687
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:810
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:698
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:665
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:869
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:938
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1020
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1102
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:690
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:756
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:801
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:742
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:769
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:661
+coverage: 98.732%	pattern: 126	before: 63	now: 63
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1095
+coverage: 98.753%	pattern: 127	before: 63	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:805
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:692
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:773
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1414
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1243
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:910
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:664
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:808
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:670
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1092
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:786
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:789
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:956
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1259
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:639
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:815
+coverage: 98.753%	pattern: 127	before: 62	now: 62
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:666
+coverage: 98.773%	pattern: 128	before: 62	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:694
+coverage: 98.773%	pattern: 128	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:803
+coverage: 98.773%	pattern: 128	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:803
+coverage: 98.773%	pattern: 128	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1109
+coverage: 98.773%	pattern: 128	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:761
+coverage: 98.773%	pattern: 128	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:726
+coverage: 98.773%	pattern: 128	before: 61	now: 61
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1229
+coverage: 98.813%	pattern: 129	before: 61	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:671
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:670
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:787
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:661
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:658
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:793
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:769
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:671
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:716
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:807
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:699
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1070
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:769
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:697
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:779
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:797
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1159
+coverage: 98.813%	pattern: 129	before: 59	now: 59
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1269
+coverage: 98.853%	pattern: 130	before: 59	now: 57
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:693
+coverage: 98.853%	pattern: 130	before: 57	now: 57
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:814
+coverage: 98.853%	pattern: 130	before: 57	now: 57
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:810
+coverage: 98.853%	pattern: 130	before: 57	now: 57
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:869
+coverage: 98.913%	pattern: 131	before: 57	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:761
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:773
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:663
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:712
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:797
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:654
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:782
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:805
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:722
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:742
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:810
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:831
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:756
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:823
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:688
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:787
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:760
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:715
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1151
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:966
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:801
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:781
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:817
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:694
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:679
+coverage: 98.913%	pattern: 131	before: 54	now: 54
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:816
+coverage: 98.934%	pattern: 132	before: 54	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:691
+coverage: 98.934%	pattern: 132	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:656
+coverage: 98.934%	pattern: 132	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:662
+coverage: 98.934%	pattern: 132	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:867
+coverage: 98.934%	pattern: 132	before: 53	now: 53
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 984, fault_cnt:1115
+coverage: 98.994%	pattern: 133	before: 53	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:667
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:757
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:788
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:677
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:812
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:742
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:817
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:806
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1084
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:775
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:963
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:721
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1018
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:708
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:790
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:704
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:834
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:743
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:963
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:679
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:806
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:653
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:764
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:778
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:671
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:837
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:647
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:788
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:634
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:654
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:678
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:727
+coverage: 98.994%	pattern: 133	before: 50	now: 50
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1137
+coverage: 99.014%	pattern: 134	before: 50	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:808
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:686
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:833
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:665
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:794
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:770
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:687
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1195
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1068
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:778
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:726
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:964
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:724
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:792
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:679
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:733
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1029
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:865
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:717
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:677
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:752
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:817
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1209
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:766
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:715
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1279
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:782
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:800
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:767
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:806
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:922
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1278
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:982
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:680
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1141
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:726
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:757
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:862
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1111
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:691
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:857
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:809
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:864
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:707
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:929
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:762
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:766
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:686
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:672
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:742
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:685
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:784
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:819
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:951
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:764
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:806
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:757
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:765
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1097
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:674
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:687
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:786
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:668
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:968
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:628
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:855
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:678
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:829
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1065
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:655
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1265
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:645
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:642
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:772
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:760
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:683
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:781
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:875
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:799
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1084
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1167
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1022
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:679
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1321
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:803
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:780
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:759
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:681
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:754
+coverage: 99.014%	pattern: 134	before: 49	now: 49
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1296
+coverage: 99.054%	pattern: 135	before: 49	now: 47
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:677
+coverage: 99.054%	pattern: 135	before: 47	now: 47
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1331
+coverage: 99.095%	pattern: 136	before: 47	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:809
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:769
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:740
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:797
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:700
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:793
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:708
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:755
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:641
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:669
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:789
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:675
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:798
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1244
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1079
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:803
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:963
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:776
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:655
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:714
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:804
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:989
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:786
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:658
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:704
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1102
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:916
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:706
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1004
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1019
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:773
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:777
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:929
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:823
+coverage: 99.095%	pattern: 136	before: 45	now: 45
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 984, fault_cnt:1176
+coverage: 99.135%	pattern: 137	before: 45	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:821
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:834
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:704
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:655
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1153
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:658
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:800
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:782
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:619
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:678
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:631
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:826
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1063
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:938
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1227
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1021
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:749
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:653
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:764
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:900
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:966
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:756
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1080
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:757
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:765
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:690
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:683
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:999
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1041
+coverage: 99.135%	pattern: 137	before: 43	now: 43
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:1297
+coverage: 99.155%	pattern: 138	before: 43	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:807
+coverage: 99.155%	pattern: 138	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:989
+coverage: 99.155%	pattern: 138	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1078
+coverage: 99.155%	pattern: 138	before: 42	now: 42
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 984, fault_cnt:806
+coverage: 99.175%	pattern: 139	before: 42	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:728
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:824
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1255
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:780
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:734
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1144
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:820
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:781
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:798
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1149
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1104
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:667
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:966
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:800
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:698
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:1087
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:731
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:780
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:766
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 984, fault_cnt:661
+coverage: 99.175%	pattern: 139	before: 41	now: 41
+checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_c6288.bench.txt b/exp_result/ATPG-LS_c6288.bench.txt
index c7aa804..a3f83ee 100644
--- a/exp_result/ATPG-LS_c6288.bench.txt
+++ b/exp_result/ATPG-LS_c6288.bench.txt
@@ -8,612 +8,492 @@ Gate:	2448
 Stem:	1488
 Level:	7
 ================================ 
-[SOL] flip: 0, stem: 0, fault:41910. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2217
-coverage: 45.282%	pattern: 1	before: 4896	now: 2679
+[SOL] flip: 0, stem: 0, fault:41770. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
+coverage: 44.914%	pattern: 1	before: 4896	now: 2697
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:21592. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
-coverage: 68.566%	pattern: 2	before: 2679	now: 1539
+[SOL] flip: 0, stem: 0, fault:17100. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
+coverage: 63.297%	pattern: 2	before: 2697	now: 1797
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:11922. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206
-coverage: 81.536%	pattern: 3	before: 1539	now: 904
+[SOL] flip: 0, stem: 0, fault:12844. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205
+coverage: 77.104%	pattern: 3	before: 1797	now: 1121
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5196. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
-coverage: 87.132%	pattern: 4	before: 904	now: 630
+[SOL] flip: 0, stem: 0, fault:7239. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
+coverage: 84.886%	pattern: 4	before: 1121	now: 740
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4078. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
-coverage: 91.585%	pattern: 5	before: 630	now: 412
+[SOL] flip: 0, stem: 0, fault:4275. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
+coverage: 89.481%	pattern: 5	before: 740	now: 515
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1786. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
-coverage: 93.505%	pattern: 6	before: 412	now: 318
+[SOL] flip: 0, stem: 0, fault:2660. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
+coverage: 92.341%	pattern: 6	before: 515	now: 375
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1178. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
-coverage: 94.771%	pattern: 7	before: 318	now: 256
+[SOL] flip: 0, stem: 0, fault:1634. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 94.097%	pattern: 7	before: 375	now: 289
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:798. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
-coverage: 95.629%	pattern: 8	before: 256	now: 214
+[SOL] flip: 0, stem: 0, fault:1121. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
+coverage: 95.302%	pattern: 8	before: 289	now: 230
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:646. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 96.324%	pattern: 9	before: 214	now: 180
+[SOL] flip: 0, stem: 0, fault:665. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
+coverage: 96.017%	pattern: 9	before: 230	now: 195
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2145
-coverage: 97.426%	pattern: 10	before: 180	now: 126
+[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
+coverage: 97.038%	pattern: 10	before: 195	now: 145
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 97.896%	pattern: 11	before: 126	now: 103
+[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2167
+coverage: 97.447%	pattern: 11	before: 145	now: 125
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206
-coverage: 98.019%	pattern: 12	before: 103	now: 97
+[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
+coverage: 97.876%	pattern: 12	before: 125	now: 104
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
-coverage: 98.223%	pattern: 13	before: 97	now: 87
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2207
+coverage: 98.080%	pattern: 13	before: 104	now: 94
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
-coverage: 98.448%	pattern: 14	before: 87	now: 76
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2208
+coverage: 98.284%	pattern: 14	before: 94	now: 84
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
-coverage: 98.754%	pattern: 15	before: 76	now: 61
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
+coverage: 98.366%	pattern: 15	before: 84	now: 80
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
-coverage: 99.020%	pattern: 16	before: 61	now: 48
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173
+coverage: 98.529%	pattern: 16	before: 80	now: 72
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
-coverage: 99.183%	pattern: 17	before: 48	now: 40
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
+coverage: 98.754%	pattern: 17	before: 72	now: 61
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
-coverage: 99.244%	pattern: 18	before: 40	now: 37
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 98.775%	pattern: 18	before: 61	now: 60
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
-coverage: 99.306%	pattern: 19	before: 37	now: 34
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
+coverage: 98.958%	pattern: 19	before: 60	now: 51
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
+coverage: 99.040%	pattern: 20	before: 51	now: 47
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
+coverage: 99.163%	pattern: 21	before: 47	now: 41
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
-coverage: 99.367%	pattern: 20	before: 34	now: 31
+coverage: 99.224%	pattern: 22	before: 41	now: 38
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2168
-coverage: 99.449%	pattern: 21	before: 31	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.469%	pattern: 22	before: 27	now: 26
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
-coverage: 99.489%	pattern: 23	before: 26	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2160
-coverage: 99.510%	pattern: 24	before: 25	now: 24
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
-coverage: 99.510%	pattern: 24	before: 24	now: 24
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
-coverage: 99.571%	pattern: 25	before: 24	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.571%	pattern: 25	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.571%	pattern: 25	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
-coverage: 99.571%	pattern: 25	before: 21	now: 21
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.632%	pattern: 26	before: 21	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
-coverage: 99.632%	pattern: 26	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
-coverage: 99.632%	pattern: 26	before: 18	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
-coverage: 99.653%	pattern: 27	before: 18	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2167
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2158
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2166
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2169
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2211
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
+coverage: 99.265%	pattern: 23	before: 38	now: 36
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2221
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2176
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2157
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2170
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2209
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.265%	pattern: 23	before: 36	now: 36
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.265%	pattern: 23	before: 36	now: 36
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2229
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2212
+coverage: 99.285%	pattern: 24	before: 36	now: 35
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2215
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
+coverage: 99.326%	pattern: 25	before: 35	now: 33
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.367%	pattern: 26	before: 33	now: 31
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
+coverage: 99.387%	pattern: 27	before: 31	now: 30
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.387%	pattern: 27	before: 30	now: 30
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2161
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2162
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2164
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2171
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2167
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2163
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2235
+coverage: 99.408%	pattern: 28	before: 30	now: 29
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.408%	pattern: 28	before: 29	now: 29
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
+coverage: 99.428%	pattern: 29	before: 29	now: 28
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2163
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2164
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2216
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2176
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.449%	pattern: 30	before: 28	now: 27
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2212
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.449%	pattern: 30	before: 27	now: 27
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.449%	pattern: 30	before: 27	now: 27
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.449%	pattern: 30	before: 27	now: 27
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2207
+coverage: 99.489%	pattern: 31	before: 27	now: 25
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.530%	pattern: 32	before: 25	now: 23
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
+coverage: 99.551%	pattern: 33	before: 23	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.551%	pattern: 33	before: 22	now: 22
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
+coverage: 99.571%	pattern: 34	before: 22	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
+coverage: 99.571%	pattern: 34	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2233
+coverage: 99.571%	pattern: 34	before: 21	now: 21
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
-coverage: 99.653%	pattern: 27	before: 17	now: 17
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.571%	pattern: 34	before: 21	now: 21
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.571%	pattern: 34	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
+coverage: 99.571%	pattern: 34	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
+coverage: 99.571%	pattern: 34	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
+coverage: 99.571%	pattern: 34	before: 21	now: 21
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
+coverage: 99.592%	pattern: 35	before: 21	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2223
+coverage: 99.592%	pattern: 35	before: 20	now: 20
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.592%	pattern: 35	before: 20	now: 20
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2208
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2162
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
+coverage: 99.592%	pattern: 35	before: 20	now: 20
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
-coverage: 99.653%	pattern: 27	before: 17	now: 17
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2212
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2209
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210
+coverage: 99.592%	pattern: 35	before: 20	now: 20
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2231
+coverage: 99.612%	pattern: 36	before: 20	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2215
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
+coverage: 99.612%	pattern: 36	before: 19	now: 19
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
+coverage: 99.653%	pattern: 37	before: 19	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2209
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2172
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2213
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2224
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2216
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2170
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181
+coverage: 99.653%	pattern: 37	before: 17	now: 17
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190
+coverage: 99.653%	pattern: 37	before: 17	now: 17
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_c7552.bench.txt b/exp_result/ATPG-LS_c7552.bench.txt
index 037778d..9af4176 100644
--- a/exp_result/ATPG-LS_c7552.bench.txt
+++ b/exp_result/ATPG-LS_c7552.bench.txt
@@ -8,663 +8,1932 @@ Gate:	3719
 Stem:	1537
 Level:	10
 ================================ 
-[SOL] flip: 0, stem: 0, fault:31574. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1667
-coverage: 22.412%	pattern: 1	before: 7438	now: 5771
+[SOL] flip: 0, stem: 0, fault:26624. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1413
+coverage: 18.997%	pattern: 1	before: 7438	now: 6025
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:23913. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1701
-coverage: 40.656%	pattern: 2	before: 5771	now: 4414
+[SOL] flip: 0, stem: 0, fault:21122. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1740
+coverage: 34.149%	pattern: 2	before: 6025	now: 4898
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:13051. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593
-coverage: 50.094%	pattern: 3	before: 4414	now: 3712
+[SOL] flip: 0, stem: 0, fault:7932. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484
+coverage: 40.199%	pattern: 3	before: 4898	now: 4448
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:5949. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
-coverage: 54.329%	pattern: 4	before: 3712	now: 3397
+[SOL] flip: 0, stem: 0, fault:8685. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482
+coverage: 46.491%	pattern: 4	before: 4448	now: 3980
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:6654. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
-coverage: 59.196%	pattern: 5	before: 3397	now: 3035
+[SOL] flip: 0, stem: 0, fault:6199. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1429
+coverage: 50.901%	pattern: 5	before: 3980	now: 3652
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4089. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1580
-coverage: 62.140%	pattern: 6	before: 3035	now: 2816
+[SOL] flip: 0, stem: 0, fault:4890. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1565
+coverage: 54.369%	pattern: 6	before: 3652	now: 3394
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:3109. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1443
-coverage: 64.372%	pattern: 7	before: 2816	now: 2650
+[SOL] flip: 0, stem: 0, fault:5742. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1591
+coverage: 58.457%	pattern: 7	before: 3394	now: 3090
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:6042. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1750
-coverage: 68.647%	pattern: 8	before: 2650	now: 2332
+[SOL] flip: 0, stem: 0, fault:4304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1610
+coverage: 61.589%	pattern: 8	before: 3090	now: 2857
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:4459. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1716
-coverage: 71.847%	pattern: 9	before: 2332	now: 2094
+[SOL] flip: 0, stem: 0, fault:2698. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1547
+coverage: 63.498%	pattern: 9	before: 2857	now: 2715
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1653. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
-coverage: 73.017%	pattern: 10	before: 2094	now: 2007
+[SOL] flip: 0, stem: 0, fault:4898. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1678
+coverage: 67.021%	pattern: 10	before: 2715	now: 2453
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1121. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1430
-coverage: 73.810%	pattern: 11	before: 2007	now: 1948
+[SOL] flip: 0, stem: 0, fault:2812. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1628
+coverage: 69.010%	pattern: 11	before: 2453	now: 2305
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:7467. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2099
-coverage: 79.094%	pattern: 12	before: 1948	now: 1555
+[SOL] flip: 0, stem: 0, fault:1333. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526
+coverage: 69.965%	pattern: 12	before: 2305	now: 2234
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522
-coverage: 79.766%	pattern: 13	before: 1555	now: 1505
+[SOL] flip: 0, stem: 0, fault:2603. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1643
+coverage: 71.807%	pattern: 13	before: 2234	now: 2097
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1594
-coverage: 80.438%	pattern: 14	before: 1505	now: 1455
+[SOL] flip: 0, stem: 0, fault:1672. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1485
+coverage: 72.990%	pattern: 14	before: 2097	now: 2009
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1676. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1648
-coverage: 81.675%	pattern: 15	before: 1455	now: 1363
+[SOL] flip: 0, stem: 0, fault:2831. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1613
+coverage: 74.993%	pattern: 15	before: 2009	now: 1860
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:951. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
-coverage: 82.361%	pattern: 16	before: 1363	now: 1312
+[SOL] flip: 0, stem: 0, fault:703. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1434
+coverage: 75.491%	pattern: 16	before: 1860	now: 1823
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1634. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1681
-coverage: 83.517%	pattern: 17	before: 1312	now: 1226
+[SOL] flip: 0, stem: 0, fault:1596. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1584
+coverage: 76.620%	pattern: 17	before: 1823	now: 1739
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1450
-coverage: 84.041%	pattern: 18	before: 1226	now: 1187
+[SOL] flip: 0, stem: 0, fault:2414. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1696
+coverage: 78.341%	pattern: 18	before: 1739	now: 1611
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1442
-coverage: 84.136%	pattern: 19	before: 1187	now: 1180
+[SOL] flip: 0, stem: 0, fault:1064. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555
+coverage: 79.094%	pattern: 19	before: 1611	now: 1555
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453
-coverage: 84.364%	pattern: 20	before: 1180	now: 1163
+[SOL] flip: 0, stem: 0, fault:1805. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1738
+coverage: 80.371%	pattern: 20	before: 1555	now: 1460
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:855. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1559
-coverage: 84.969%	pattern: 21	before: 1163	now: 1118
+[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1507
+coverage: 80.653%	pattern: 21	before: 1460	now: 1439
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1178. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1681
-coverage: 85.803%	pattern: 22	before: 1118	now: 1056
+[SOL] flip: 0, stem: 0, fault:3800. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1881
+coverage: 83.342%	pattern: 22	before: 1439	now: 1239
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1426
-coverage: 85.803%	pattern: 22	before: 1056	now: 1056
+[SOL] flip: 0, stem: 0, fault:96. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
+coverage: 83.423%	pattern: 23	before: 1239	now: 1233
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1007. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1759
-coverage: 86.515%	pattern: 23	before: 1056	now: 1003
+[SOL] flip: 0, stem: 0, fault:665. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526
+coverage: 83.894%	pattern: 24	before: 1233	now: 1198
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1412
-coverage: 86.636%	pattern: 24	before: 1003	now: 994
+[SOL] flip: 0, stem: 0, fault:665. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1509
+coverage: 84.364%	pattern: 25	before: 1198	now: 1163
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487
-coverage: 86.650%	pattern: 25	before: 994	now: 993
+[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1570
+coverage: 84.714%	pattern: 26	before: 1163	now: 1137
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1565
-coverage: 86.959%	pattern: 26	before: 993	now: 970
+[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1417
+coverage: 85.023%	pattern: 27	before: 1137	now: 1114
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
-coverage: 86.986%	pattern: 27	before: 970	now: 968
+[SOL] flip: 0, stem: 0, fault:551. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1524
+coverage: 85.413%	pattern: 28	before: 1114	now: 1085
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1410
-coverage: 87.161%	pattern: 28	before: 968	now: 955
+[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1642
+coverage: 86.085%	pattern: 29	before: 1085	now: 1035
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:589. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582
-coverage: 87.577%	pattern: 29	before: 955	now: 924
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1479
+coverage: 86.179%	pattern: 30	before: 1035	now: 1028
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482
-coverage: 87.591%	pattern: 30	before: 924	now: 923
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1523
+coverage: 86.287%	pattern: 31	before: 1028	now: 1020
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1508
-coverage: 87.927%	pattern: 31	before: 923	now: 898
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
+coverage: 86.314%	pattern: 32	before: 1020	now: 1018
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1509
-coverage: 87.981%	pattern: 32	before: 898	now: 894
+[SOL] flip: 0, stem: 0, fault:988. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1818
+coverage: 87.013%	pattern: 33	before: 1018	now: 966
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1609
-coverage: 88.196%	pattern: 33	before: 894	now: 878
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1459
+coverage: 87.013%	pattern: 33	before: 966	now: 966
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
-coverage: 88.518%	pattern: 34	before: 878	now: 854
+[SOL] flip: 0, stem: 0, fault:570. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1558
+coverage: 87.416%	pattern: 34	before: 966	now: 936
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1064. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1930
-coverage: 89.271%	pattern: 35	before: 854	now: 798
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1488
+coverage: 87.524%	pattern: 35	before: 936	now: 928
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1542
-coverage: 89.567%	pattern: 36	before: 798	now: 776
+[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1617
+coverage: 87.779%	pattern: 36	before: 928	now: 909
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1546
-coverage: 89.836%	pattern: 37	before: 776	now: 756
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1638
+coverage: 87.994%	pattern: 37	before: 909	now: 893
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1877
-coverage: 90.038%	pattern: 38	before: 756	now: 741
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1442
+coverage: 87.994%	pattern: 37	before: 893	now: 893
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1523
-coverage: 90.266%	pattern: 39	before: 741	now: 724
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1744
+coverage: 88.155%	pattern: 38	before: 893	now: 881
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1468
-coverage: 90.266%	pattern: 39	before: 724	now: 724
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526
+coverage: 88.196%	pattern: 39	before: 881	now: 878
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1836
-coverage: 90.589%	pattern: 40	before: 724	now: 700
+[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1749
+coverage: 88.478%	pattern: 40	before: 878	now: 857
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527
-coverage: 90.643%	pattern: 41	before: 700	now: 696
+[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1531
+coverage: 88.747%	pattern: 41	before: 857	now: 837
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1632
-coverage: 90.925%	pattern: 42	before: 696	now: 675
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499
+coverage: 88.841%	pattern: 42	before: 837	now: 830
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1829
-coverage: 91.449%	pattern: 43	before: 675	now: 636
+[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1642
+coverage: 89.029%	pattern: 43	before: 830	now: 816
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1530
-coverage: 91.517%	pattern: 44	before: 636	now: 631
+[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1751
+coverage: 89.406%	pattern: 44	before: 816	now: 788
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1653
-coverage: 91.543%	pattern: 45	before: 631	now: 629
+[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537
+coverage: 89.527%	pattern: 45	before: 788	now: 779
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1950
-coverage: 91.772%	pattern: 46	before: 629	now: 612
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593
+coverage: 89.688%	pattern: 46	before: 779	now: 767
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
-coverage: 91.812%	pattern: 47	before: 612	now: 609
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473
+coverage: 89.769%	pattern: 47	before: 767	now: 761
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534
-coverage: 91.853%	pattern: 48	before: 609	now: 606
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1547
+coverage: 89.849%	pattern: 48	before: 761	now: 755
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537
-coverage: 91.960%	pattern: 49	before: 606	now: 598
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463
+coverage: 89.876%	pattern: 49	before: 755	now: 753
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579
-coverage: 91.974%	pattern: 50	before: 598	now: 597
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1505
+coverage: 90.024%	pattern: 50	before: 753	now: 742
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
-coverage: 91.974%	pattern: 50	before: 597	now: 597
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1423
+coverage: 90.051%	pattern: 51	before: 742	now: 740
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1645
-coverage: 92.001%	pattern: 51	before: 597	now: 595
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1577
+coverage: 90.199%	pattern: 52	before: 740	now: 729
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465
-coverage: 92.001%	pattern: 51	before: 595	now: 595
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1477
+coverage: 90.239%	pattern: 53	before: 729	now: 726
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1585
-coverage: 92.108%	pattern: 52	before: 595	now: 587
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1456
+coverage: 90.239%	pattern: 53	before: 726	now: 726
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1862
-coverage: 92.135%	pattern: 53	before: 587	now: 585
+[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1477
+coverage: 90.481%	pattern: 54	before: 726	now: 708
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1505
-coverage: 92.202%	pattern: 54	before: 585	now: 580
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1698
+coverage: 90.696%	pattern: 55	before: 708	now: 692
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486
-coverage: 92.283%	pattern: 55	before: 580	now: 574
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472
+coverage: 90.750%	pattern: 56	before: 692	now: 688
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1435
-coverage: 92.283%	pattern: 55	before: 574	now: 574
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1627
+coverage: 90.844%	pattern: 57	before: 688	now: 681
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1423
-coverage: 92.350%	pattern: 56	before: 574	now: 569
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1763
-coverage: 92.404%	pattern: 57	before: 569	now: 565
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868
-coverage: 92.511%	pattern: 58	before: 565	now: 557
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1436
-coverage: 92.511%	pattern: 58	before: 557	now: 557
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419
-coverage: 92.511%	pattern: 58	before: 557	now: 557
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1666
-coverage: 92.525%	pattern: 59	before: 557	now: 556
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1564
-coverage: 92.552%	pattern: 60	before: 556	now: 554
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
-coverage: 92.606%	pattern: 61	before: 554	now: 550
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1655
-coverage: 92.673%	pattern: 62	before: 550	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1607
-coverage: 92.673%	pattern: 62	before: 545	now: 545
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2158
-coverage: 93.009%	pattern: 63	before: 545	now: 520
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1497
-coverage: 93.036%	pattern: 64	before: 520	now: 518
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658
-coverage: 93.076%	pattern: 65	before: 518	now: 515
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1833
-coverage: 93.076%	pattern: 65	before: 515	now: 515
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470
-coverage: 93.076%	pattern: 65	before: 515	now: 515
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1603
-coverage: 93.170%	pattern: 66	before: 515	now: 508
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1562
-coverage: 93.197%	pattern: 67	before: 508	now: 506
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1866
-coverage: 93.197%	pattern: 67	before: 506	now: 506
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1837
-coverage: 93.211%	pattern: 68	before: 506	now: 505
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1634
-coverage: 93.278%	pattern: 69	before: 505	now: 500
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1725
-coverage: 93.318%	pattern: 70	before: 500	now: 497
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582
-coverage: 93.332%	pattern: 71	before: 497	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1477
-coverage: 93.332%	pattern: 71	before: 496	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1427
-coverage: 93.332%	pattern: 71	before: 496	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1645
-coverage: 93.332%	pattern: 71	before: 496	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1462
-coverage: 93.332%	pattern: 71	before: 496	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1796
-coverage: 93.332%	pattern: 71	before: 496	now: 496
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1657
-coverage: 93.439%	pattern: 72	before: 496	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473
-coverage: 93.439%	pattern: 72	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526
-coverage: 93.439%	pattern: 72	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1571
-coverage: 93.439%	pattern: 72	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1449
-coverage: 93.439%	pattern: 72	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1583
-coverage: 93.439%	pattern: 72	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499
-coverage: 93.439%	pattern: 72	before: 488	now: 488
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1690
-coverage: 93.560%	pattern: 73	before: 488	now: 479
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1587
-coverage: 93.614%	pattern: 74	before: 479	now: 475
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543
-coverage: 93.614%	pattern: 74	before: 475	now: 475
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1457
-coverage: 93.614%	pattern: 74	before: 475	now: 475
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513
-coverage: 93.654%	pattern: 75	before: 475	now: 472
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1425
-coverage: 93.654%	pattern: 75	before: 472	now: 472
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1876
-coverage: 93.708%	pattern: 76	before: 472	now: 468
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1778
-coverage: 93.708%	pattern: 76	before: 468	now: 468
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1431
-coverage: 93.721%	pattern: 77	before: 468	now: 467
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
-coverage: 93.775%	pattern: 78	before: 467	now: 463
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1481
-coverage: 93.802%	pattern: 79	before: 463	now: 461
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592
-coverage: 93.802%	pattern: 79	before: 461	now: 461
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1804
-coverage: 93.802%	pattern: 79	before: 461	now: 461
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1605
-coverage: 93.816%	pattern: 80	before: 461	now: 460
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1668
-coverage: 93.842%	pattern: 81	before: 460	now: 458
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1840
-coverage: 93.842%	pattern: 81	before: 458	now: 458
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
-coverage: 93.842%	pattern: 81	before: 458	now: 458
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1662
-coverage: 93.869%	pattern: 82	before: 458	now: 456
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452
-coverage: 93.869%	pattern: 82	before: 456	now: 456
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1448
-coverage: 93.869%	pattern: 82	before: 456	now: 456
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592
-coverage: 93.869%	pattern: 82	before: 456	now: 456
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529
-coverage: 93.869%	pattern: 82	before: 456	now: 456
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1575
-coverage: 93.896%	pattern: 83	before: 456	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555
-coverage: 93.896%	pattern: 83	before: 454	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
-coverage: 93.896%	pattern: 83	before: 454	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606
-coverage: 93.896%	pattern: 83	before: 454	now: 454
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529
-coverage: 93.923%	pattern: 84	before: 454	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572
-coverage: 93.923%	pattern: 84	before: 452	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1506
-coverage: 93.923%	pattern: 84	before: 452	now: 452
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1544
-coverage: 94.152%	pattern: 85	before: 452	now: 435
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
-coverage: 94.152%	pattern: 85	before: 435	now: 435
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487
-coverage: 94.152%	pattern: 85	before: 435	now: 435
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572
-coverage: 94.152%	pattern: 85	before: 435	now: 435
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1944
-coverage: 94.367%	pattern: 86	before: 435	now: 419
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555
-coverage: 94.367%	pattern: 86	before: 419	now: 419
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453
-coverage: 94.367%	pattern: 86	before: 419	now: 419
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1828
-coverage: 94.367%	pattern: 86	before: 419	now: 419
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1570
-coverage: 94.407%	pattern: 87	before: 419	now: 416
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1760
-coverage: 94.434%	pattern: 88	before: 416	now: 414
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478
-coverage: 94.434%	pattern: 88	before: 414	now: 414
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486
-coverage: 94.434%	pattern: 88	before: 414	now: 414
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478
-coverage: 94.474%	pattern: 89	before: 414	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1512
-coverage: 94.474%	pattern: 89	before: 411	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463
-coverage: 94.474%	pattern: 89	before: 411	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1469
-coverage: 94.474%	pattern: 89	before: 411	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1621
-coverage: 94.474%	pattern: 89	before: 411	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658
-coverage: 94.474%	pattern: 89	before: 411	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1428
-coverage: 94.474%	pattern: 89	before: 411	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1568
-coverage: 94.474%	pattern: 89	before: 411	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868
-coverage: 94.474%	pattern: 89	before: 411	now: 411
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593
-coverage: 94.568%	pattern: 90	before: 411	now: 404
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1520
-coverage: 94.568%	pattern: 90	before: 404	now: 404
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1638
-coverage: 94.568%	pattern: 90	before: 404	now: 404
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527
-coverage: 94.568%	pattern: 90	before: 404	now: 404
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1458
-coverage: 94.568%	pattern: 90	before: 404	now: 404
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534
-coverage: 94.568%	pattern: 90	before: 404	now: 404
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1876
-coverage: 94.568%	pattern: 90	before: 404	now: 404
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
-coverage: 94.568%	pattern: 90	before: 404	now: 404
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1502
-coverage: 94.595%	pattern: 91	before: 404	now: 402
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1616
-coverage: 94.595%	pattern: 91	before: 402	now: 402
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
-coverage: 94.622%	pattern: 92	before: 402	now: 400
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868
-coverage: 94.622%	pattern: 92	before: 400	now: 400
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1746
-coverage: 94.622%	pattern: 92	before: 400	now: 400
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537
-coverage: 94.622%	pattern: 92	before: 400	now: 400
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1514
-coverage: 94.622%	pattern: 92	before: 400	now: 400
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484
-coverage: 94.622%	pattern: 92	before: 400	now: 400
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1627
-coverage: 94.622%	pattern: 92	before: 400	now: 400
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1566
-coverage: 94.649%	pattern: 93	before: 400	now: 398
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472
-coverage: 94.649%	pattern: 93	before: 398	now: 398
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1931
-coverage: 94.824%	pattern: 94	before: 398	now: 385
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1464
-coverage: 94.824%	pattern: 94	before: 385	now: 385
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1535
-coverage: 94.824%	pattern: 94	before: 385	now: 385
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1591
-coverage: 94.824%	pattern: 94	before: 385	now: 385
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606
-coverage: 94.824%	pattern: 94	before: 385	now: 385
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452
-coverage: 94.824%	pattern: 94	before: 385	now: 385
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1820
-coverage: 94.851%	pattern: 95	before: 385	now: 383
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1717
-coverage: 94.864%	pattern: 96	before: 383	now: 382
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1742
-coverage: 94.878%	pattern: 97	before: 382	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1474
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1878
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1577
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1897
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1576
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1607
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473
-coverage: 94.878%	pattern: 97	before: 381	now: 381
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543
-coverage: 94.905%	pattern: 98	before: 381	now: 379
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482
-coverage: 94.905%	pattern: 98	before: 379	now: 379
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465
-coverage: 94.905%	pattern: 98	before: 379	now: 379
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1910
-coverage: 95.066%	pattern: 99	before: 379	now: 367
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1437
-coverage: 95.066%	pattern: 99	before: 367	now: 367
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1698
-coverage: 95.066%	pattern: 99	before: 367	now: 367
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1495
-coverage: 95.079%	pattern: 100	before: 367	now: 366
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419
-coverage: 95.079%	pattern: 100	before: 366	now: 366
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1550
-coverage: 95.079%	pattern: 100	before: 366	now: 366
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1826
-coverage: 95.079%	pattern: 100	before: 366	now: 366
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1712
-coverage: 95.079%	pattern: 100	before: 366	now: 366
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
-coverage: 95.079%	pattern: 100	before: 366	now: 366
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1492
-coverage: 95.106%	pattern: 101	before: 366	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1869
-coverage: 95.106%	pattern: 101	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499
-coverage: 95.106%	pattern: 101	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529
-coverage: 95.106%	pattern: 101	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1510
-coverage: 95.106%	pattern: 101	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1578
-coverage: 95.106%	pattern: 101	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1878
-coverage: 95.106%	pattern: 101	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470
-coverage: 95.106%	pattern: 101	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1563
-coverage: 95.106%	pattern: 101	before: 364	now: 364
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1637
-coverage: 95.120%	pattern: 102	before: 364	now: 363
+[SOL] flip: 0, stem: 0, fault:760. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2033
+coverage: 91.382%	pattern: 58	before: 681	now: 641
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1444
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+coverage: 91.382%	pattern: 58	before: 641	now: 641
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1544
+coverage: 91.409%	pattern: 59	before: 641	now: 639
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1783
+coverage: 91.624%	pattern: 60	before: 639	now: 623
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1945
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522
+coverage: 91.691%	pattern: 61	before: 623	now: 618
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1623
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1426
+coverage: 91.718%	pattern: 62	before: 618	now: 616
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1684
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1586
+coverage: 91.880%	pattern: 63	before: 616	now: 604
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1539
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1575
+coverage: 91.880%	pattern: 63	before: 604	now: 604
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1519
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1444
+coverage: 91.906%	pattern: 64	before: 604	now: 602
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1853
+coverage: 91.974%	pattern: 65	before: 602	now: 597
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1500
+coverage: 92.001%	pattern: 66	before: 597	now: 595
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1628
+coverage: 92.068%	pattern: 67	before: 595	now: 590
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1517
+coverage: 92.135%	pattern: 68	before: 590	now: 585
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1492
+coverage: 92.229%	pattern: 69	before: 585	now: 578
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1459
+coverage: 92.229%	pattern: 69	before: 578	now: 578
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1485
+coverage: 92.229%	pattern: 69	before: 578	now: 578
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1900
+coverage: 92.377%	pattern: 70	before: 578	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1438
+coverage: 92.377%	pattern: 70	before: 567	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1524
+coverage: 92.377%	pattern: 70	before: 567	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
+coverage: 92.377%	pattern: 70	before: 567	now: 567
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555
+coverage: 92.390%	pattern: 71	before: 567	now: 566
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527
+coverage: 92.404%	pattern: 72	before: 566	now: 565
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
+coverage: 92.417%	pattern: 73	before: 565	now: 564
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1481
+coverage: 92.417%	pattern: 73	before: 564	now: 564
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1578
+coverage: 92.417%	pattern: 73	before: 564	now: 564
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1535
+coverage: 92.417%	pattern: 73	before: 564	now: 564
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1548
+coverage: 92.458%	pattern: 74	before: 564	now: 561
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1565
+coverage: 92.485%	pattern: 75	before: 561	now: 559
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1454
+coverage: 92.525%	pattern: 76	before: 559	now: 556
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1692
+coverage: 92.565%	pattern: 77	before: 556	now: 553
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1518
+coverage: 92.606%	pattern: 78	before: 553	now: 550
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1642
+coverage: 92.632%	pattern: 79	before: 550	now: 548
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1450
+coverage: 92.632%	pattern: 79	before: 548	now: 548
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1947
+coverage: 92.727%	pattern: 80	before: 548	now: 541
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1442
+coverage: 92.727%	pattern: 80	before: 541	now: 541
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522
+coverage: 92.753%	pattern: 81	before: 541	now: 539
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1523
+coverage: 92.780%	pattern: 82	before: 539	now: 537
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1682
+coverage: 93.305%	pattern: 83	before: 537	now: 498
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1632
+coverage: 93.305%	pattern: 83	before: 498	now: 498
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534
+coverage: 93.318%	pattern: 84	before: 498	now: 497
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1475
+coverage: 93.412%	pattern: 85	before: 497	now: 490
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1477
+coverage: 93.412%	pattern: 85	before: 490	now: 490
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472
+coverage: 93.412%	pattern: 85	before: 490	now: 490
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1490
+coverage: 93.439%	pattern: 86	before: 490	now: 488
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1496
+coverage: 93.439%	pattern: 86	before: 488	now: 488
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1812
+coverage: 93.493%	pattern: 87	before: 488	now: 484
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582
+coverage: 93.520%	pattern: 88	before: 484	now: 482
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1647
+coverage: 93.600%	pattern: 89	before: 482	now: 476
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1542
+coverage: 93.600%	pattern: 89	before: 476	now: 476
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1565
+coverage: 93.600%	pattern: 89	before: 476	now: 476
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1427
+coverage: 93.600%	pattern: 89	before: 476	now: 476
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1481
+coverage: 93.627%	pattern: 90	before: 476	now: 474
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1461
+coverage: 93.695%	pattern: 91	before: 474	now: 469
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1574
+coverage: 93.695%	pattern: 91	before: 469	now: 469
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1548
+coverage: 93.695%	pattern: 91	before: 469	now: 469
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1861
+coverage: 93.695%	pattern: 91	before: 469	now: 469
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1567
+coverage: 93.721%	pattern: 92	before: 469	now: 467
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1755
+coverage: 93.748%	pattern: 93	before: 467	now: 465
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1621
+coverage: 93.802%	pattern: 94	before: 465	now: 461
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1485
+coverage: 93.802%	pattern: 94	before: 461	now: 461
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1600
+coverage: 93.856%	pattern: 95	before: 461	now: 457
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579
+coverage: 93.883%	pattern: 96	before: 457	now: 455
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1761
+coverage: 93.937%	pattern: 97	before: 455	now: 451
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1432
+coverage: 93.937%	pattern: 97	before: 451	now: 451
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1425
+coverage: 93.937%	pattern: 97	before: 451	now: 451
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1893
+coverage: 93.977%	pattern: 98	before: 451	now: 448
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1421
+coverage: 93.977%	pattern: 98	before: 448	now: 448
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1462
+coverage: 93.990%	pattern: 99	before: 448	now: 447
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452
+coverage: 93.990%	pattern: 99	before: 447	now: 447
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1864
+coverage: 93.990%	pattern: 99	before: 447	now: 447
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1633
+coverage: 94.017%	pattern: 100	before: 447	now: 445
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1834
+coverage: 94.017%	pattern: 100	before: 445	now: 445
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1903
+coverage: 94.017%	pattern: 100	before: 445	now: 445
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1425
+coverage: 94.017%	pattern: 100	before: 445	now: 445
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1525
+coverage: 94.017%	pattern: 100	before: 445	now: 445
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1490
+coverage: 94.017%	pattern: 100	before: 445	now: 445
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1540
+coverage: 94.044%	pattern: 101	before: 445	now: 443
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+coverage: 94.044%	pattern: 101	before: 443	now: 443
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1409
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1564
+coverage: 94.044%	pattern: 101	before: 443	now: 443
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1512
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1521
+coverage: 94.071%	pattern: 102	before: 443	now: 441
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1836
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1446
+coverage: 94.071%	pattern: 102	before: 441	now: 441
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1600
+coverage: 94.071%	pattern: 102	before: 441	now: 441
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1466
+coverage: 94.125%	pattern: 103	before: 441	now: 437
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1545
+coverage: 94.125%	pattern: 103	before: 437	now: 437
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1556
-coverage: 95.120%	pattern: 102	before: 363	now: 363
+coverage: 94.125%	pattern: 103	before: 437	now: 437
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1646
-coverage: 95.133%	pattern: 103	before: 363	now: 362
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1590
+coverage: 94.125%	pattern: 103	before: 437	now: 437
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593
+coverage: 94.125%	pattern: 103	before: 437	now: 437
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1450
+coverage: 94.125%	pattern: 103	before: 437	now: 437
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419
+coverage: 94.125%	pattern: 103	before: 437	now: 437
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1585
+coverage: 94.125%	pattern: 103	before: 437	now: 437
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1567
+coverage: 94.125%	pattern: 103	before: 437	now: 437
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1824
+coverage: 94.138%	pattern: 104	before: 437	now: 436
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1496
+coverage: 94.138%	pattern: 104	before: 436	now: 436
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
+coverage: 94.138%	pattern: 104	before: 436	now: 436
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1640
+coverage: 94.165%	pattern: 105	before: 436	now: 434
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1577
+coverage: 94.165%	pattern: 105	before: 434	now: 434
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2151
+coverage: 94.192%	pattern: 106	before: 434	now: 432
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1646
+coverage: 94.219%	pattern: 107	before: 432	now: 430
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484
+coverage: 94.246%	pattern: 108	before: 430	now: 428
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
+coverage: 94.246%	pattern: 108	before: 428	now: 428
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1519
+coverage: 94.246%	pattern: 108	before: 428	now: 428
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1894
+coverage: 94.286%	pattern: 109	before: 428	now: 425
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1611
+coverage: 94.286%	pattern: 109	before: 425	now: 425
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1548
+coverage: 94.286%	pattern: 109	before: 425	now: 425
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1589
+coverage: 94.286%	pattern: 109	before: 425	now: 425
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1725
+coverage: 94.326%	pattern: 110	before: 425	now: 422
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465
+coverage: 94.326%	pattern: 110	before: 422	now: 422
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1624
+coverage: 94.326%	pattern: 110	before: 422	now: 422
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527
-coverage: 95.133%	pattern: 103	before: 362	now: 362
+coverage: 94.326%	pattern: 110	before: 422	now: 422
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1819
+coverage: 94.326%	pattern: 110	before: 422	now: 422
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513
+coverage: 94.380%	pattern: 111	before: 422	now: 418
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1459
+coverage: 94.380%	pattern: 111	before: 418	now: 418
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1737
+coverage: 94.380%	pattern: 111	before: 418	now: 418
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1450
+coverage: 94.407%	pattern: 112	before: 418	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1454
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1816
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1515
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1594
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1550
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2149
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1436
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1471
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1717
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1435
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1433
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1616
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1446
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1502
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1457
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1471
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1570
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1420
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1623
+coverage: 94.407%	pattern: 112	before: 416	now: 416
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1804
+coverage: 94.461%	pattern: 113	before: 416	now: 412
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
+coverage: 94.515%	pattern: 114	before: 412	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1457
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1575
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1536
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1443
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2011
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1468
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1506
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1502
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1430
+coverage: 94.515%	pattern: 114	before: 408	now: 408
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526
+coverage: 94.582%	pattern: 115	before: 408	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1547
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1750
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1701
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1468
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1492
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1560
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1460
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1467
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1712
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1518
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1533
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1622
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1418
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1462
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1450
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1539
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1552
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1562
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1533
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1432
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1425
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1518
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1517
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1446
+coverage: 94.582%	pattern: 115	before: 403	now: 403
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
+coverage: 94.595%	pattern: 116	before: 403	now: 402
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592
+coverage: 94.595%	pattern: 116	before: 402	now: 402
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1505
+coverage: 94.595%	pattern: 116	before: 402	now: 402
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1455
+coverage: 94.595%	pattern: 116	before: 402	now: 402
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606
+coverage: 94.595%	pattern: 116	before: 402	now: 402
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1498
+coverage: 94.595%	pattern: 116	before: 402	now: 402
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1835
+coverage: 94.609%	pattern: 117	before: 402	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1751
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1586
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1500
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1528
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1844
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1844
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1515
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1922
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1509
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1423
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1532
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1489
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1508
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1462
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1710
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1560
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1540
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1538
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1871
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1662
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1600
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1624
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1559
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1775
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1770
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1449
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1434
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1568
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1648
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1485
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1436
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1521
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1415
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1732
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1480
+coverage: 94.609%	pattern: 117	before: 401	now: 401
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1811
+coverage: 94.622%	pattern: 118	before: 401	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579
+coverage: 94.622%	pattern: 118	before: 400	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537
+coverage: 94.622%	pattern: 118	before: 400	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1559
+coverage: 94.622%	pattern: 118	before: 400	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1695
+coverage: 94.622%	pattern: 118	before: 400	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1704
+coverage: 94.622%	pattern: 118	before: 400	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1613
+coverage: 94.622%	pattern: 118	before: 400	now: 400
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1603
+coverage: 94.649%	pattern: 119	before: 400	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1430
+coverage: 94.649%	pattern: 119	before: 398	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1510
+coverage: 94.649%	pattern: 119	before: 398	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1635
+coverage: 94.649%	pattern: 119	before: 398	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1662
+coverage: 94.649%	pattern: 119	before: 398	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486
+coverage: 94.649%	pattern: 119	before: 398	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1418
+coverage: 94.649%	pattern: 119	before: 398	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1495
+coverage: 94.649%	pattern: 119	before: 398	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1523
+coverage: 94.649%	pattern: 119	before: 398	now: 398
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522
+coverage: 94.757%	pattern: 120	before: 398	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1524
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1578
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2157
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1559
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1500
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1569
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1617
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1772
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1549
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1538
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1847
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1425
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1410
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1611
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1546
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1448
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1455
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1558
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1597
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1535
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1590
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1533
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1429
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1800
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1442
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1507
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1451
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1505
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1502
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1518
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1422
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1481
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1468
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1587
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1764
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1454
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1976
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1597
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1590
+coverage: 94.757%	pattern: 120	before: 390	now: 390
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1517
+coverage: 94.891%	pattern: 121	before: 390	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1427
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1562
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1547
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1624
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1458
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1798
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1428
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1424
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1444
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1515
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1826
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1520
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1476
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1528
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1497
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1443
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1481
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1553
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1467
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1843
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1536
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1530
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1416
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1438
+coverage: 94.891%	pattern: 121	before: 380	now: 380
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1603
+coverage: 94.945%	pattern: 122	before: 380	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1530
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1474
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1865
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1495
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1835
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1642
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1589
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1479
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1422
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1436
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1568
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1434
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1449
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1584
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1504
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1571
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1860
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1456
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1541
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1556
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1518
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1414
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1510
+coverage: 94.945%	pattern: 122	before: 376	now: 376
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1683
+coverage: 95.147%	pattern: 123	before: 376	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1411
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1550
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1733
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1557
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1549
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1557
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1542
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1506
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1659
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1443
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1560
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1445
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453
+coverage: 95.147%	pattern: 123	before: 361	now: 361
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593
+coverage: 95.200%	pattern: 124	before: 361	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1553
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1426
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1670
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1586
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1477
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1508
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1700
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534
+coverage: 95.200%	pattern: 124	before: 357	now: 357
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1642
+coverage: 95.214%	pattern: 125	before: 357	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1500
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1585
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1933
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1488
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1517
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1504
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1833
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1557
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1731
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1430
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1588
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1560
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1422
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1398
+coverage: 95.214%	pattern: 125	before: 356	now: 356
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452
+coverage: 95.254%	pattern: 126	before: 356	now: 353
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1460
+coverage: 95.254%	pattern: 126	before: 353	now: 353
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1559
+coverage: 95.254%	pattern: 126	before: 353	now: 353
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
+coverage: 95.254%	pattern: 126	before: 353	now: 353
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1896
+coverage: 95.268%	pattern: 127	before: 353	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1576
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1916
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1544
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1485
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1712
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1428
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1601
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1640
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1462
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1449
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1456
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1458
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1492
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1749
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1520
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1520
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1416
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1412
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1446
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1421
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1550
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1652
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1570
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1581
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1447
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1466
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1423
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1430
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1751
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1578
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1517
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1700
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1442
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1735
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1568
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1456
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1467
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1524
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1602
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1583
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1476
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1420
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1491
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1794
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1544
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1504
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1485
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1521
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1446
+coverage: 95.268%	pattern: 127	before: 352	now: 352
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1515
+coverage: 95.375%	pattern: 128	before: 352	now: 344
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1530
+coverage: 95.375%	pattern: 128	before: 344	now: 344
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1437
+coverage: 95.375%	pattern: 128	before: 344	now: 344
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1623
+coverage: 95.375%	pattern: 128	before: 344	now: 344
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1525
+coverage: 95.375%	pattern: 128	before: 344	now: 344
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1587
+coverage: 95.483%	pattern: 129	before: 344	now: 336
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1432
+coverage: 95.483%	pattern: 129	before: 336	now: 336
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1449
+coverage: 95.483%	pattern: 129	before: 336	now: 336
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1542
+coverage: 95.483%	pattern: 129	before: 336	now: 336
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1861
+coverage: 95.671%	pattern: 130	before: 336	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1511
+coverage: 95.671%	pattern: 130	before: 322	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1433
+coverage: 95.671%	pattern: 130	before: 322	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1564
+coverage: 95.671%	pattern: 130	before: 322	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1521
+coverage: 95.671%	pattern: 130	before: 322	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1748
+coverage: 95.671%	pattern: 130	before: 322	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513
+coverage: 95.671%	pattern: 130	before: 322	now: 322
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1697
+coverage: 95.684%	pattern: 131	before: 322	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1601
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1532
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1479
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1536
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1467
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1475
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1432
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1590
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1648
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1386
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1451
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1585
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1437
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1447
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1492
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1724
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1457
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1424
+coverage: 95.684%	pattern: 131	before: 321	now: 321
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1661
+coverage: 95.738%	pattern: 132	before: 321	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1508
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1497
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1596
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1874
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1557
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1626
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1821
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1898
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1552
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1539
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1479
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1531
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1531
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1666
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1420
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1528
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1746
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1716
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1439
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1553
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1528
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1496
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1847
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1651
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1420
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1626
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1525
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1566
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1858
+coverage: 95.738%	pattern: 132	before: 317	now: 317
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1659
+coverage: 95.778%	pattern: 133	before: 317	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1564
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1833
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1575
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1506
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1600
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1580
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1447
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1808
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1553
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1530
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1497
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1459
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1464
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1515
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1598
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1502
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1402
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1854
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1937
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1570
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1693
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1412
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1673
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1713
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1581
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1528
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1585
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1523
+coverage: 95.778%	pattern: 133	before: 314	now: 314
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1476
+coverage: 95.832%	pattern: 134	before: 314	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1844
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1469
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1501
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1922
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1723
+coverage: 95.832%	pattern: 134	before: 310	now: 310
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1599
+coverage: 95.832%	pattern: 134	before: 310	now: 310
 checking valid circuit ... result: 1.
diff --git a/exp_result/ATPG-LS_c880.bench.txt b/exp_result/ATPG-LS_c880.bench.txt
index 1dae541..6ac1e0d 100644
--- a/exp_result/ATPG-LS_c880.bench.txt
+++ b/exp_result/ATPG-LS_c880.bench.txt
@@ -8,2701 +8,523 @@ Gate:	443
 Stem:	165
 Level:	6
 ================================ 
-[SOL] flip: 0, stem: 0, fault:5605. flip_cnt: 0, stem_cnt: 165, fault_cnt:295
-coverage: 33.296%	pattern: 1	before: 886	now: 591
+[SOL] flip: 0, stem: 0, fault:2949. flip_cnt: 0, stem_cnt: 165, fault_cnt:256
+coverage: 28.894%	pattern: 1	before: 886	now: 630
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:3325. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 53.047%	pattern: 2	before: 591	now: 416
+[SOL] flip: 0, stem: 0, fault:2909. flip_cnt: 0, stem_cnt: 165, fault_cnt:319
+coverage: 56.321%	pattern: 2	before: 630	now: 387
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:1520. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 62.077%	pattern: 3	before: 416	now: 336
+[SOL] flip: 0, stem: 0, fault:738. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
+coverage: 64.447%	pattern: 3	before: 387	now: 315
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:2014. flip_cnt: 0, stem_cnt: 165, fault_cnt:298
-coverage: 74.041%	pattern: 4	before: 336	now: 230
+[SOL] flip: 0, stem: 0, fault:1090. flip_cnt: 0, stem_cnt: 165, fault_cnt:288
+coverage: 73.589%	pattern: 4	before: 315	now: 234
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 76.524%	pattern: 5	before: 230	now: 208
+[SOL] flip: 0, stem: 0, fault:453. flip_cnt: 0, stem_cnt: 165, fault_cnt:272
+coverage: 78.217%	pattern: 5	before: 234	now: 193
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:565. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 81.151%	pattern: 6	before: 208	now: 167
+[SOL] flip: 0, stem: 0, fault:680. flip_cnt: 0, stem_cnt: 165, fault_cnt:293
+coverage: 82.957%	pattern: 6	before: 193	now: 151
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 82.167%	pattern: 7	before: 167	now: 158
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:175
+coverage: 83.521%	pattern: 7	before: 151	now: 146
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 84.650%	pattern: 8	before: 158	now: 136
+[SOL] flip: 0, stem: 0, fault:34. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
+coverage: 83.973%	pattern: 8	before: 146	now: 142
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 86.117%	pattern: 9	before: 136	now: 123
+[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
+coverage: 86.230%	pattern: 9	before: 142	now: 122
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 165, fault_cnt:199
-coverage: 87.020%	pattern: 10	before: 123	now: 115
+[SOL] flip: 0, stem: 0, fault:197. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
+coverage: 87.810%	pattern: 10	before: 122	now: 108
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 87.133%	pattern: 11	before: 115	now: 114
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 87.923%	pattern: 12	before: 114	now: 107
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 88.939%	pattern: 13	before: 107	now: 98
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
-coverage: 90.519%	pattern: 14	before: 98	now: 84
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 165, fault_cnt:261
-coverage: 91.986%	pattern: 15	before: 84	now: 71
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 92.551%	pattern: 16	before: 71	now: 66
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 92.664%	pattern: 17	before: 66	now: 65
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
-coverage: 93.002%	pattern: 18	before: 65	now: 62
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:187
-coverage: 93.002%	pattern: 18	before: 62	now: 62
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
-coverage: 94.018%	pattern: 19	before: 62	now: 53
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:286
-coverage: 94.244%	pattern: 20	before: 53	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194
-coverage: 94.244%	pattern: 20	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:187
-coverage: 94.244%	pattern: 20	before: 51	now: 51
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 165, fault_cnt:336
-coverage: 94.695%	pattern: 21	before: 51	now: 47
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 165, fault_cnt:291
-coverage: 95.147%	pattern: 22	before: 47	now: 43
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 95.485%	pattern: 23	before: 43	now: 40
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:192
-coverage: 95.711%	pattern: 24	before: 40	now: 38
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:284
-coverage: 95.937%	pattern: 25	before: 38	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:271
-coverage: 95.937%	pattern: 25	before: 36	now: 36
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 96.050%	pattern: 26	before: 36	now: 35
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
-coverage: 96.275%	pattern: 27	before: 35	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 96.275%	pattern: 27	before: 33	now: 33
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 96.840%	pattern: 28	before: 33	now: 28
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 96.953%	pattern: 29	before: 28	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 96.953%	pattern: 29	before: 27	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 96.953%	pattern: 29	before: 27	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 96.953%	pattern: 29	before: 27	now: 27
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 97.178%	pattern: 30	before: 27	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191
-coverage: 97.178%	pattern: 30	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 97.178%	pattern: 30	before: 25	now: 25
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 165, fault_cnt:333
-coverage: 97.968%	pattern: 31	before: 25	now: 18
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 97.968%	pattern: 31	before: 18	now: 18
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:266
+coverage: 87.923%	pattern: 11	before: 108	now: 107
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283
-coverage: 97.968%	pattern: 31	before: 18	now: 18
+coverage: 87.923%	pattern: 11	before: 107	now: 107
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 97.968%	pattern: 31	before: 18	now: 18
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
+coverage: 88.488%	pattern: 12	before: 107	now: 102
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 97.968%	pattern: 31	before: 18	now: 18
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
+coverage: 88.713%	pattern: 13	before: 102	now: 100
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 97.968%	pattern: 31	before: 18	now: 18
+[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
+coverage: 89.278%	pattern: 14	before: 100	now: 95
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
-coverage: 97.968%	pattern: 31	before: 18	now: 18
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:170
+coverage: 89.391%	pattern: 15	before: 95	now: 94
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 97.968%	pattern: 31	before: 18	now: 18
+[SOL] flip: 0, stem: 0, fault:237. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
+coverage: 90.858%	pattern: 16	before: 94	now: 81
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
-coverage: 98.194%	pattern: 32	before: 18	now: 16
+[SOL] flip: 0, stem: 0, fault:183. flip_cnt: 0, stem_cnt: 165, fault_cnt:204
+coverage: 93.002%	pattern: 17	before: 81	now: 62
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195
-coverage: 98.194%	pattern: 32	before: 16	now: 16
+[SOL] flip: 0, stem: 0, fault:102. flip_cnt: 0, stem_cnt: 165, fault_cnt:284
+coverage: 94.018%	pattern: 18	before: 62	now: 53
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 98.307%	pattern: 33	before: 16	now: 15
+[SOL] flip: 0, stem: 0, fault:137. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
+coverage: 95.372%	pattern: 19	before: 53	now: 41
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 98.307%	pattern: 33	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
+coverage: 95.598%	pattern: 20	before: 41	now: 39
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 98.307%	pattern: 33	before: 15	now: 15
+[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
+coverage: 96.388%	pattern: 21	before: 39	now: 32
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
-coverage: 98.307%	pattern: 33	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
-coverage: 98.307%	pattern: 33	before: 15	now: 15
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 98.420%	pattern: 34	before: 15	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:159
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 98.420%	pattern: 34	before: 14	now: 14
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 98.420%	pattern: 34	before: 14	now: 14
+[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
+coverage: 96.614%	pattern: 22	before: 32	now: 30
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
-coverage: 98.533%	pattern: 35	before: 14	now: 13
+coverage: 96.727%	pattern: 23	before: 30	now: 29
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 98.533%	pattern: 35	before: 13	now: 13
+[SOL] flip: 0, stem: 0, fault:40. flip_cnt: 0, stem_cnt: 165, fault_cnt:318
+coverage: 97.178%	pattern: 24	before: 29	now: 25
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 98.533%	pattern: 35	before: 13	now: 13
+[SOL] flip: 0, stem: 0, fault:50. flip_cnt: 0, stem_cnt: 165, fault_cnt:186
+coverage: 97.743%	pattern: 25	before: 25	now: 20
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
-coverage: 98.646%	pattern: 36	before: 13	now: 12
+[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
+coverage: 98.081%	pattern: 26	before: 20	now: 17
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:303
-coverage: 98.758%	pattern: 37	before: 12	now: 11
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
+coverage: 98.307%	pattern: 27	before: 17	now: 15
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 98.758%	pattern: 37	before: 11	now: 11
+[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
+coverage: 98.420%	pattern: 28	before: 15	now: 14
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 98.758%	pattern: 37	before: 11	now: 11
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
+coverage: 98.420%	pattern: 28	before: 14	now: 14
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 98.758%	pattern: 37	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 98.758%	pattern: 37	before: 11	now: 11
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 98.871%	pattern: 38	before: 11	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:170
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:298
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:299
-coverage: 98.871%	pattern: 38	before: 10	now: 10
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:308
-coverage: 98.984%	pattern: 39	before: 10	now: 9
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
+coverage: 98.533%	pattern: 29	before: 14	now: 13
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+coverage: 98.533%	pattern: 29	before: 13	now: 13
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
+coverage: 98.533%	pattern: 29	before: 13	now: 13
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:34. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
+coverage: 98.758%	pattern: 30	before: 13	now: 11
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
+coverage: 98.758%	pattern: 30	before: 11	now: 11
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
+coverage: 98.758%	pattern: 30	before: 11	now: 11
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:267
+coverage: 98.984%	pattern: 31	before: 11	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
+coverage: 98.984%	pattern: 31	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
+coverage: 98.984%	pattern: 31	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197
+coverage: 98.984%	pattern: 31	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
+coverage: 98.984%	pattern: 31	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 98.984%	pattern: 39	before: 9	now: 9
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
+coverage: 98.984%	pattern: 31	before: 9	now: 9
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:21. flip_cnt: 0, stem_cnt: 165, fault_cnt:182
-coverage: 99.210%	pattern: 40	before: 9	now: 7
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
+coverage: 99.210%	pattern: 32	before: 9	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:184
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.210%	pattern: 40	before: 7	now: 7
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:313
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:286
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:198
-coverage: 99.210%	pattern: 40	before: 7	now: 7
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:308
-coverage: 99.436%	pattern: 41	before: 7	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:170
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:316
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:179
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.436%	pattern: 41	before: 5	now: 5
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.661%	pattern: 42	before: 5	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:190
-coverage: 99.661%	pattern: 42	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
-coverage: 99.661%	pattern: 42	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185
-coverage: 99.661%	pattern: 42	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:291
-coverage: 99.661%	pattern: 42	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.661%	pattern: 42	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283
-coverage: 99.661%	pattern: 42	before: 3	now: 3
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 99.774%	pattern: 43	before: 3	now: 2
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 99.774%	pattern: 43	before: 2	now: 2
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:292
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:317
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:297
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.774%	pattern: 43	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:330
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:292
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:184
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:204
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207
-coverage: 99.774%	pattern: 43	before: 2	now: 2
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:179
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:302
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:167
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:315
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:280
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:186
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:278
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:284
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:169
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:159
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:275
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.774%	pattern: 43	before: 2	now: 2
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200
-coverage: 99.774%	pattern: 43	before: 2	now: 2
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:296
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:281
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:271
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:204
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:179
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:349
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.774%	pattern: 43	before: 2	now: 2
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:182
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:198
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:311
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:172
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:173
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:284
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:172
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:280
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 99.774%	pattern: 43	before: 2	now: 2
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
-coverage: 99.887%	pattern: 44	before: 2	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:315
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:192
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:178
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:284
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:306
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:287
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:164
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:196
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:270
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:196
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:177
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:271
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:204
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:297
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:271
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:186
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:323
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:198
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:176
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:173
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:166
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:171
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:281
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:166
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:300
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:287
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:308
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:179
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:275
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:286
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:340
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:278
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:184
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:174
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:270
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:161
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:281
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:266
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:204
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:183
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:289
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:198
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:275
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:176
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:314
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:192
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.210%	pattern: 32	before: 7	now: 7
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:163
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:310
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265
+coverage: 99.210%	pattern: 32	before: 7	now: 7
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
+coverage: 99.323%	pattern: 33	before: 7	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:288
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
+coverage: 99.323%	pattern: 33	before: 6	now: 6
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:301
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:170
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:318
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:270
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:299
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:280
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:175
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:190
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:167
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:196
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:180
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:270
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:256
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:335
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:169
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:163
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.323%	pattern: 33	before: 6	now: 6
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 165, fault_cnt:198
+coverage: 99.436%	pattern: 34	before: 6	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:192
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:294
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:300
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:312
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:178
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:162
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:292
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:165
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:303
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:278
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:163
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:281
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234
-coverage: 99.887%	pattern: 44	before: 1	now: 1
-checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:285
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:298
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:167
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:278
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
 [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
-coverage: 99.887%	pattern: 44	before: 1	now: 1
+coverage: 99.436%	pattern: 34	before: 5	now: 5
 checking valid circuit ... result: 1.
-[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:235
-coverage: 100.000%	pattern: 45	before: 1	now: 0
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
+coverage: 99.436%	pattern: 34	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
+coverage: 99.436%	pattern: 34	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:287
+coverage: 99.436%	pattern: 34	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
+coverage: 99.436%	pattern: 34	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218
+coverage: 99.436%	pattern: 34	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259
+coverage: 99.436%	pattern: 34	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257
+coverage: 99.436%	pattern: 34	before: 5	now: 5
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:285
+coverage: 99.549%	pattern: 35	before: 5	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:327
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:286
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:172
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:304
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:172
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:293
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:164
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205
+coverage: 99.549%	pattern: 35	before: 4	now: 4
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:33. flip_cnt: 0, stem_cnt: 165, fault_cnt:270
+coverage: 99.774%	pattern: 36	before: 4	now: 2
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 165, fault_cnt:295
+coverage: 99.887%	pattern: 37	before: 2	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:182
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185
+coverage: 99.887%	pattern: 37	before: 1	now: 1
+checking valid circuit ... result: 1.
+[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 165, fault_cnt:229
+coverage: 100.000%	pattern: 38	before: 1	now: 0
 checking valid circuit ... result: 1.
 
-real	7m21.840s
-user	7m21.806s
-sys	0m0.012s
+real	0m13.726s
+user	0m13.723s
+sys	0m0.000s
diff --git a/ls.cpp b/ls.cpp
index 21e164a..5ca1487 100644
--- a/ls.cpp
+++ b/ls.cpp
@@ -109,7 +109,7 @@ bool Circuit::local_search(std::unordered_set<Fault*> &faults) {
                 CC[suc->id] = 1;
             }
 
-            printf("[UP] flip: %lld, stem: %lld, fault:%lld. flip_cnt: %lld, stem_cnt: %lld, fault_cnt:%lld\n", flip_total_weight, stem_total_weight, fault_total_weight, flip_total_cnt, stem_total_cnt, fault_total_cnt);
+            //printf("[UP] flip: %lld, stem: %lld, fault:%lld. flip_cnt: %lld, stem_cnt: %lld, fault_cnt:%lld\n", flip_total_weight, stem_total_weight, fault_total_weight, flip_total_cnt, stem_total_cnt, fault_total_cnt);
         }
     }
 
diff --git a/report/atpg-ls-动态增量.txt b/report/atpg-ls-动态增量.txt
new file mode 100644
index 0000000..a27c943
--- /dev/null
+++ b/report/atpg-ls-动态增量.txt
@@ -0,0 +1,30 @@
+--------------------------------------------------------------------------------------------------------------
+| data                    | fault coverage(ATPG-LS) | time(ATPG-LS)       | cube(ATPG-LS) | pattern(ATPG-LS) | 
+| ----------------------- | ----------------------- | ------------------- | ------------- | ---------------- | 
+| ./benchmark/c17.bench   | 100.000                 | 0.11560654640197754 | 4             | 4                | 
+| ./benchmark/b06.bench   | 100.000                 | 0.11869049072265625 | 10            | 10               | 
+| ./benchmark/b01.bench   | 100.000                 | 0.3559579849243164  | 13            | 13               | 
+| ./benchmark/b03.bench   | 100.000                 | 0.8975160121917725  | 13            | 13               | 
+| ./benchmark/b09.bench   | 100.000                 | 6.73541784286499    | 20            | 20               | 
+| ./benchmark/c880.bench  | 100.000                 | 13.738963603973389  | 38            | 38               | 
+| ./benchmark/b10.bench   | 100.000                 | 13.915901899337769  | 31            | 31               | 
+| ./benchmark/b08.bench   | 100.000                 | 44.885215282440186  | 36            | 36               | 
+| ./benchmark/c499.bench  | 100.000                 | 72.9014344215393    | 59            | 59               | 
+| ./benchmark/c1355.bench | 100.000                 | 354.89149928092957  | 93            | 93               | 
+| ./benchmark/c3540.bench | 92.932                  | 2000.0045857429504  | 126           | 126              | 
+| ./benchmark/c1908.bench | 99.452                  | 2000.0044167041779  | 85            | 85               | 
+| ./benchmark/b11.bench   | 98.485                  | 2000.0039746761322  | 59            | 59               | 
+| ./benchmark/c6288.bench | 99.653                  | 2000.005141735077   | 37            | 37               | 
+| ./benchmark/c2670.bench | 94.881                  | 2000.0041010379791  | 75            | 75               | 
+| ./benchmark/b21.bench   | 45.309                  | 2000.031025648117   | 21            | 21               | 
+| ./benchmark/b13.bench   | 98.602                  | 2000.030693769455   | 30            | 30               | 
+| ./benchmark/b22.bench   | 30.701                  | 2000.1147837638855  | 4             | 4                | 
+| ./benchmark/b17.bench   | ERROR                   | 2000.1162934303284  | ERROR         | ERROR            | 
+| ./benchmark/b20.bench   | 48.958                  | 2000.1155791282654  | 19            | 19               | 
+| ./benchmark/c7552.bench | 95.832                  | 2000.1170272827148  | 134           | 134              | 
+| ./benchmark/b12.bench   | 94.418                  | 2000.1147434711456  | 123           | 123              | 
+| ./benchmark/c5315.bench | 99.175                  | 2000.1144452095032  | 139           | 139              | 
+| ./benchmark/b04.bench   | 99.659                  | 2000.1151909828186  | 50            | 50               | 
+| ./benchmark/b07.bench   | 98.687                  | 2000.1153008937836  | 34            | 34               | 
+| ./benchmark/c432.bench  | 99.235                  | 2000.1161303520203  | 28            | 28               | 
+--------------------------------------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/run_exp.py b/run_exp.py
index 08b62a2..8114a78 100644
--- a/run_exp.py
+++ b/run_exp.py
@@ -186,9 +186,9 @@ def multiprocess_run_solver(solver, input_file):
     (path, filename) = os.path.split(input_file)
     out_file = os.path.join(res_dir,"%s_%s.txt" % (solver.name, filename))
 
-    #(status, time) = solver.run(input_file, out_file, TIMEOUT)
-    time = "-*-"
-    status = ExitStatus.normal
+    (status, time) = solver.run(input_file, out_file, TIMEOUT)
+    # time = "-*-"
+    # status = ExitStatus.normal
 
     fault = "-*-"
     cube = "-*-"